Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   PWM using FPGA (http://www.velocityreviews.com/forums/t23088-pwm-using-fpga.html)

iceman 11-13-2004 02:25 PM

PWM using FPGA
 
does anyone have a code for this? i will be using pwm for controlling
a servo motor..

Leon Heller 11-13-2004 07:59 PM

Re: PWM using FPGA
 
"iceman" <static123ph@yahoo.com> wrote in message
news:62011d8f.0411130625.2702975@posting.google.co m...
> does anyone have a code for this? i will be using pwm for controlling
> a servo motor..


There is some VHDL code for driving model control servos in "Rapid
Prototyping of Digital Systems" by Hamblen and Furman. It's on the CD-ROM
that comes with the book.

Leon



Jonathan Bromley 11-14-2004 12:30 AM

Re: PWM using FPGA
 
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<419667b5$0$20216$cc9e4d1f@news-text.dial.pipex.com>...
> "iceman" <static123ph@yahoo.com> wrote in message
> news:62011d8f.0411130625.2702975@posting.google.co m...
> > does anyone have a code for this? i will be using pwm for controlling
> > a servo motor..

>
> There is some VHDL code for driving model control servos in "Rapid
> Prototyping of Digital Systems" by Hamblen and Furman. It's on the CD-ROM
> that comes with the book.


My colleague Bert Cuzeau has done a nice description of simple
motor control techniques:
http://www.alse-fr.com/English/ApNote204189.pdf

and a Google search through the comp.lang.vhdl archives will
turn up several discussions of the same topic.
--
Jonathan Bromley

krithika211 02-01-2009 03:04 PM

spwm using fpga
 
hi i am doing a project fpga based speed control of ac servomotor using SPWM.i need the vhdl coding for this. someone please help.

jeppe 02-01-2009 09:53 PM

Actually do you have two choises - PWM and PPM

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PWM_vs_Sigma_Delta_v2 is
    generic( N:  natural := 4;
                  Max: natural := 16);
    Port ( Clk :  in  STD_LOGIC;
                Scale: in  STD_LOGIC;
          PCM :  in  STD_LOGIC_VECTOR (N-1 downto 0);
          PWM :  out  STD_LOGIC;
          PPM :  out  STD_LOGIC);  -- or SD
end PWM_vs_Sigma_Delta_v2;

ARCHITECTURE Behavioral of PWM_vs_Sigma_Delta_v2 is
  signal PWM_Count:  STD_LOGIC_VECTOR (N-1 downto 0) := (others=>'0');
  signal Sigma:                  STD_LOGIC_VECTOR (  N downto 0) := (others=>'0');
  signal Delta:                  STD_LOGIC_VECTOR (  N downto 0) := (others=>'0');
        signal Scaled_clk: STD_LOGIC;       
begin

  process( Clk, Scale)
                variable Scalex:            integer;
                constant Scale100msek: integer  :=  1; --5000;
                constant Scale500msek: integer  :=  0; --25000;
                variable Count:  integer range 0 to 50000001 := 0;
        begin         
          if Scale='1' then
        Scalex := Scale100msek;
                else
        Scalex := Scale500msek;
                end if;
               
          if rising_edge(Clk)then
                        if Count>=Scalex then
                          Scaled_clk <= '1';
                                Count      := 0;
                        else
                          Scaled_clk <= '0';
                                Count      := Count+1;                       
                        end if;
                end if;
  end process;
       
        PWM_Generator: process( Clk, PWM_Count, PCM)
        begin
          if rising_edge(Clk) then
                  if Scaled_Clk='1' then
                          if PWM_Count<Max-1 then
                        PWM_Count <= PWM_Count+1;
                                else
              PWM_Count <= (others => '0');       
            end if;                                       
                        end if;
                end if;
         
          if PWM_Count<PCM then
                  PWM <= '1';
                else
                  PWM <= '0';
                end if;
        end process PWM_Generator;       
       
        Delta <= '0'&PCM;       
  Sigma_Delta_Generator: process( Clk)
        begin
          if rising_edge(Clk) then
                  if Scaled_Clk='1' then
                                if Sigma<Max then
                                        PPM  <= '0';
                                        Sigma <= Sigma+Delta;       
                                else
                                        PPM  <= '1';
                                        Sigma <= Sigma+Delta-conv_std_logic_vector(Max,N+1);
                                end if;
                        end if;
                end if;
        end process Sigma_Delta_Generator;       
               
end Behavioral;

The simulations can be seen here as well:
http://www.jjmk.dk/MMMI/Exercises/05...elta/index.htm
Your welcome
Jeppe

krithika211 02-05-2009 04:25 PM

fpga vhdl
 
hi thanks a lot for the help.but i am stil a bit confused about this code.is it vhdl code to generate SPWM signals? i have not learnt vhdl programming that is why i am unable to figure out what exactly the code is for.in my project i have to generate Sine PWM (SPWM) signals using vhdl to control speed of ac servomotor.is it possible for u to give ur email id?i may need your help.

PRASAD84 02-18-2009 06:39 PM

hi im doing project on pwm control of bldc motor using FPGA
 
Quote:

Originally Posted by krithika211
hi i am doing a project fpga based speed control of ac servomotor using SPWM.i need the vhdl coding for this. someone please help.

hi krithika im also doing project on fpga.
i have some pwm codes. it is better if we discuss about our projects .reply me at
please give me ur mail id also
prasadpabolu gmailcom
my mobile no +91 9952586864
my mail id is prasadpabolu at the rate of gmail dot com
please give me reply

necostefan 02-24-2010 12:30 PM

hi, i have too a project like yours(a pwm control of BLDC motor using FPGA) and i don't have the code for it.Please help me if you have something.Cosmin

subhash_iitr 02-25-2010 12:39 PM

I am beginner in FPGA design. I want to interface ADC no: AD7822 to virtex-5 (ML-505) kit externally.The ADC -AD7822 is a parallel ADc .Please guide me in doing this and perovide me the VHDL code for interfacing parallel ADC.
Thanks

ramteke.abhay@hotmail.com 03-09-2010 12:18 PM

hi to all
my project is to control the position of AC servo motor by sliding mode control can anybody guide me how to proceed and how i get the VHDL/verilog code for same help me if possible
thanks in advance


All times are GMT. The time now is 07:58 AM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.