||09-26-2004 11:38 PM
a Sample and hold circuit model
i am trying to model a Sample and hold device for a ADC, using
VHDL-AMS on Cadence.I used the Zero Order Hold attribute ('zoh()) to
sample the inputs. The code had no problems running on Mentor Graphics
System Vision, but when i ported the code to Cadence it did not. I
seems that the 'zoh() function is not yet built into Cadence VHDL-AMS
Now my question is that is there any equivalent function for 'zoh() ?
I have posted this query in comp.lang.cad.Cadence , but no reply as of
will be happy if somebody could clear this..
||03-05-2008 06:55 PM
I had the same problem. To addres the problem I decided to make a ZOH block.
I made the code using quantity inputs and outputs. The code was tested unsign a sinuosidal signal and it worked fine.
--- CODE OF ZOH BLOCK
ENTITY ZOHF IS
GENERIC (Ts: TIME:= 10 us);
PORT(signal clkout : out bit;
QUANTITY Vin : IN REAL:=0.0;
QUANTITY Vout: OUT REAL:=0.0);
ARCHITECTURE behavior_sampler OF ZOHF IS
shared variable Vin_HOLD : REAL:=0.0;
SIGNAL clk: bit :='1';
clock: process (clk)
clk <= not clk after Ts/2;
END PROCESS clock;
IF (clk'EVENT AND clk='1') THEN
END PROCESS samp;
LIBRARY DISCIPLINES, IEEE;
ENTITY bench IS END ENTITY bench;
ARCHITECTURE sample OF bench IS
QUANTITY vin1, n2 : REAL:=0.0;
CONSTANT f : REAL := 1.0E3;
signal clk : bit;
vin1 == 2.0;
ZOH1: ENTITY ZOHF(behavior_sampler)
GENERIC MAP (Ts => 0.05e-3 sec)
PORT MAP (clk,Vin1, n2);
END ARCHITECTURE sample;
I hope that will help you
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