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Viswan 08-03-2004 09:36 PM

doubt in VHDL
 
hi,
I have question regarding multiplication in VHDL. I have many
multiplications to be done in an application and I have only one
multiplier in my hardware. And in many of the multiplications I am
going to do, I will have either multiplicand or multiplier or both as
some constant values. Now my question is how can I load these
constants as the input to the multiplier? Do I have to use some
separate registers to hold these constants through out or can I just
use some internal signals and assign them these constant values and
use those? Once synthesized, will there be any problem if I use the
internal signals to hold the constant values?

And also any suggestion to deal with these multiplication with
constants is greatly appreciated.

Thanks
Viswan

Ralfe Cookson 08-04-2004 10:01 PM

Re: doubt in VHDL
 
viswan_1981@hotmail.com (Viswan) wrote in message news:<c9cb3993.0408031336.22a22226@posting.google. com>...
> hi,
> I have question regarding multiplication in VHDL. I have many
> multiplications to be done in an application and I have only one
> multiplier in my hardware. And in many of the multiplications I am
> going to do, I will have either multiplicand or multiplier or both as
> some constant values. Now my question is how can I load these
> constants as the input to the multiplier? Do I have to use some
> separate registers to hold these constants through out or can I just
> use some internal signals and assign them these constant values and
> use those? Once synthesized, will there be any problem if I use the
> internal signals to hold the constant values?
>
> And also any suggestion to deal with these multiplication with
> constants is greatly appreciated.
>
> Thanks
> Viswan


Your question is not very clear.

If you are multiplying A * C where A is a variable but C is a constant
(i.e. known before hand),then you do not need to tie up your
multiplier for this. You can use adders to do the multiplication
provided you shift the bits of A appropriately at the adder inputs to
do the power of 2 multiplications. For example if C = 11, then the
product in terms of power of 2 sums is 8A + 2A + A. Multiply by 8 =
shift left 3 bits. Multiply by 2 = shift left 1 bit.

So your adder's input bit triplets would be:

1A 2A 8A
-----------------
A(0) + 0 + 0
A(1) + A(0) + 0
A(2) + A(1) + 0
A(3) + A(2) + A(0)
A(4) + A(3) + A(1)
..
..
..
etc.

If you are multiplying two constants C1 * C2, just do the
multiplication in advance and hard code the product into your VHDL
code. No need for any multipliers or adders.

If you are multiplying two variables, i.e. neither is a constant, then
you should use the multiplier. If you are saying that you have several
sources for the variables and only one multiplier to multiply them,
then you need some muxes on the inputs to the multiplier to select
which operands to use and a state machine to control the select lines
of the muxes and where to store the products. You can also use this
for the constants if time is not a constraint.

Viswan 08-23-2004 10:33 PM

Re: doubt in VHDL
 
ralfe.cookson@trw.com (Ralfe Cookson) wrote in message news:<6085b684.0408041401.20f35681@posting.google. com>...
> viswan_1981@hotmail.com (Viswan) wrote in message news:<c9cb3993.0408031336.22a22226@posting.google. com>...
> > hi,
> > I have question regarding multiplication in VHDL. I have many
> > multiplications to be done in an application and I have only one
> > multiplier in my hardware. And in many of the multiplications I am
> > going to do, I will have either multiplicand or multiplier or both as
> > some constant values. Now my question is how can I load these
> > constants as the input to the multiplier? Do I have to use some
> > separate registers to hold these constants through out or can I just
> > use some internal signals and assign them these constant values and
> > use those? Once synthesized, will there be any problem if I use the
> > internal signals to hold the constant values?
> >
> > And also any suggestion to deal with these multiplication with
> > constants is greatly appreciated.
> >
> > Thanks
> > Viswan

>
> Your question is not very clear.
>
> If you are multiplying A * C where A is a variable but C is a constant
> (i.e. known before hand),then you do not need to tie up your
> multiplier for this. You can use adders to do the multiplication
> provided you shift the bits of A appropriately at the adder inputs to
> do the power of 2 multiplications. For example if C = 11, then the
> product in terms of power of 2 sums is 8A + 2A + A. Multiply by 8 =
> shift left 3 bits. Multiply by 2 = shift left 1 bit.
>
> So your adder's input bit triplets would be:
>
> 1A 2A 8A
> -----------------
> A(0) + 0 + 0
> A(1) + A(0) + 0
> A(2) + A(1) + 0
> A(3) + A(2) + A(0)
> A(4) + A(3) + A(1)
> .
> .
> .
> etc.
>
> If you are multiplying two constants C1 * C2, just do the
> multiplication in advance and hard code the product into your VHDL
> code. No need for any multipliers or adders.
>
> If you are multiplying two variables, i.e. neither is a constant, then
> you should use the multiplier. If you are saying that you have several
> sources for the variables and only one multiplier to multiply them,
> then you need some muxes on the inputs to the multiplier to select
> which operands to use and a state machine to control the select lines
> of the muxes and where to store the products. You can also use this
> for the constants if time is not a constraint.



hi,

Thanks a lot for this help. It helped me a bit. But what I was
trying to ask also is, suppose I have some constants to be used in the
operations. For example I have this X * 1.7895 ( here I am using
fixed point reals), and also I want to use multiplier only for this
purpose. While coding in VHDL can I just represent this value of
1.7895 as some 'signal' and assign this constant value to that signal
as follows:
signal exvalue : std_logic_vector (15 downto 0);
exvalue <= "0001.........1";
Regards
Viswan

Tuukka Toivonen 08-24-2004 09:44 AM

Re: doubt in VHDL
 
In article <c9cb3993.0408231433.11fd4ed6@posting.google.com >, Viswan wrote:
> purpose. While coding in VHDL can I just represent this value of
> 1.7895 as some 'signal' and assign this constant value to that signal
> as follows:
> signal exvalue : std_logic_vector (15 downto 0);
> exvalue <= "0001.........1";


Yes, you can. No synthesizer should have problems with that.

Or you could use "when" to select correct constant:

m <= "101010101" when STATE=CONST1 else "101111101";

or a "process" statement with case...end case.


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