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Heliboy 07-06-2004 06:43 AM

Xilinx FPGA routing question
 
Folks,

I have this question for a long time, just could not get an answer.

Assume we have a design consisting of several blocks and some of those
blocks are hinhly regular (for example, a datapath). When we do P&R,
does the tool take the advantage of this regularity and place those
datapath element in series? Or it just does P&R globally without
looking at the local regularity?

The reason I am asking this is that we have a design with blocks which
are regular inside. But after P&R, the LUT utilization increases
dramatically, it seems it uses lots LUT for routing which isn't
expected just by looking at the regularity of the blocks.

Thanks.

Kelvin 07-06-2004 08:44 AM

Re: Xilinx FPGA routing question
 
You may try to do some manual floor planning then let the router do the
rest...

Don't expect the machine to understand everything you know...


Kelvin







"Heliboy" <heliboy2003@yahoo.com.tw> wrote in message
news:a91f428b.0407052243.69385c03@posting.google.c om...
> Folks,
>
> I have this question for a long time, just could not get an answer.
>
> Assume we have a design consisting of several blocks and some of those
> blocks are hinhly regular (for example, a datapath). When we do P&R,
> does the tool take the advantage of this regularity and place those
> datapath element in series? Or it just does P&R globally without
> looking at the local regularity?
>
> The reason I am asking this is that we have a design with blocks which
> are regular inside. But after P&R, the LUT utilization increases
> dramatically, it seems it uses lots LUT for routing which isn't
> expected just by looking at the regularity of the blocks.
>
> Thanks.





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