Inversion of signals on synthesis
Dear Sir or Madam,
I have some phenomenon I do not know when synthesizing my VHDL
description for my
The .vho-file from Quartus is used for a timing simulation. When I
have a look at internal signals
of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar'
I see in timing simulation with Modelsim that they are right inverted
to my description, for example are
they resetted to '0' and not to my declared '1' in the VHDL
The outputs of my controller are concurrently assigned like that:
OE_bar <= l_oe_bar;
CS_bar <= l_cs_bar;
WE_bar <= l_we_bar;
And yet they are inverted to the local signals.
I do not know why there seems to be a double inversion. What does
I would appreciate your help.
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