Representing signed numbers in VHDL
is their standard way to represent signed numbers in binary? I know there is
two's complement notation etc etc. but is there a general standard to do
this in binary notation or do people tend to use two's complement?
|All times are GMT. The time now is 09:36 PM.|
Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.