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-   -   Propagation delay trought a control signal "SEL" of a MUX (http://www.velocityreviews.com/forums/t22244-propagation-delay-trought-a-control-signal-sel-of-a-mux.html)

 Oleg 02-18-2004 07:17 PM

Propagation delay trought a control signal "SEL" of a MUX

Hi

I am using synplify to synthesis my vhdl design code. the code is an
most of error correcting decoders. Lets say : the inputs are A,B,C & D
vectors the operation is : (A+B)>(C+D) the output is the result of the
smallest of (A+B) & (C+D)this is done by combinatory logic and folowed
by a D flip-flop.

Now if I synthesis this design, I obtaine fmax=150 Mhz.

Now if i add a Mux in the B and D paths so now i have a 2Mux feeding
the operations (A+B)>(C+D) whit B and D values accordantly. The
control (sel) of a MUX is kind of fix value (a config value that we
fix in the begining of simulation and we dont change it) so that way a
MUX is playing a role of a switch.

The probleme is when i synthetis this design it give me 98 Mhz.

The question is : is there any way to tel to the synthesis tool that a
control signal (sel) for the MUX's is statistic, calculate only the
propagation delay through the MUX (from the in tel the out)whitout
taking in acount propagation delay of sel. And a such way that the
synthesis tool wil not ignore a mux and will not relpace it by a
direct wire.

A,B,C & D are 8 bits , MUX is 16:1

 Francisco Rodriguez 02-18-2004 07:45 PM

Re: Propagation delay trought a control signal "SEL" of a MUX

Hi Oleg

Don't rely on the synthesis fmax estimated value, use actual fmax given by
the PAR tool.

If you're using XST, you can use the UCF file to say
NET "sel" TIG;
which basically tells the par tool to ignore all paths starting at sel

A completely different matter is if the MUX will be present in your design.
Only if there exists the possibility to change the sel value at run-time
(using an external input pad, for example) the MUX is required.
It will be trimmed otherwise.

Regards
Francisco

"Oleg" <benkhalh@hotmail.com> escribió en el mensaje
> Hi
>
> I am using synplify to synthesis my vhdl design code. the code is an
> most of error correcting decoders. Lets say : the inputs are A,B,C & D
> vectors the operation is : (A+B)>(C+D) the output is the result of the
> smallest of (A+B) & (C+D)this is done by combinatory logic and folowed
> by a D flip-flop.
>
> Now if I synthesis this design, I obtaine fmax=150 Mhz.
>
> Now if i add a Mux in the B and D paths so now i have a 2Mux feeding
> the operations (A+B)>(C+D) whit B and D values accordantly. The
> control (sel) of a MUX is kind of fix value (a config value that we
> fix in the begining of simulation and we dont change it) so that way a
> MUX is playing a role of a switch.
>
> The probleme is when i synthetis this design it give me 98 Mhz.
>
> The question is : is there any way to tel to the synthesis tool that a
> control signal (sel) for the MUX's is statistic, calculate only the
> propagation delay through the MUX (from the in tel the out)whitout
> taking in acount propagation delay of sel. And a such way that the
> synthesis tool wil not ignore a mux and will not relpace it by a
> direct wire.
>
> A,B,C & D are 8 bits , MUX is 16:1

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