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-   -   'driving_value attribute (http://www.velocityreviews.com/forums/t21969-driving_value-attribute.html)

Peter Hermansson 11-25-2003 12:05 PM

'driving_value attribute
 
Hi,

I have no luck in using the 'driving_value attribute. The following
simple code creates a "No driver in this region for 'driving or
'driving_value attribute of signal v" error message in Modelsim.

library ieee;
Use ieee.std_logic_1164.all;

Entity test Is
Port(
a : In Std_logic;
b : In Std_logic;
y : Out Std_logic;
v : Out Std_logic
);
End test;

Architecture RTL Of test Is

Begin

v <= a or b;
y <= a and v'driving_value;

End Architecture RTL;

I have activated the VHDL93 switch....
Have I misunderstood how to use this attribute?

Thanks in advance,

Peter

Jonathan Bromley 11-25-2003 06:46 PM

Re: 'driving_value attribute
 
"Peter Hermansson" <peter.hermansson@sts.saab.se> wrote in
message news:4fc631bb.0311250405.1c94755b@posting.google.c om...

> I have no luck in using the 'driving_value attribute. The following
> simple code creates a "No driver in this region for 'driving or
> 'driving_value attribute of signal v" error message in Modelsim.


[...]
> Architecture RTL Of test Is
> Begin
> v <= a or b;
> y <= a and v'driving_value;
> End Architecture RTL;


> Have I misunderstood how to use this attribute?


Yes, I think so. You have created two distinct
processes: one for the assignment to v, one for
the assignment to y. 'driving_value applies only
inside a process, where it provides visibility of
the value that THE CURRENT PROCESS is driving
on to the chosen signal.

What are you trying to do? I don't really see
what meaning you ascribe to v'driving_value in
the above code.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Mike Treseler 11-25-2003 06:56 PM

Re: 'driving_value attribute
 
Peter Hermansson wrote:
luck in using the 'driving_value attribute. The following
> simple code creates a "No driver in this region for 'driving or
> 'driving_value attribute of signal v" error message in Modelsim.
>
> library ieee;
> Use ieee.std_logic_1164.all;
> Entity test Is
> Port(
> a : In Std_logic;
> b : In Std_logic;
> y : Out Std_logic;
> v : Out Std_logic
> );
> End test;
> Architecture RTL Of test Is
> Begin
> v <= a or b;
> y <= a and v'driving_value;
> End Architecture RTL;
>
> I have activated the VHDL93 switch....
> Have I misunderstood how to use this attribute?


'driving_value is only visible inside the driving process.
So let's combine your two processes into one.

comb : process (a, b) is
begin -- process comb
v <= a or b;
y <= a and v'driving_value;
end process comb;


But consider using an explicit variable instead, like this:

library ieee;
use ieee.std_logic_1164.all;
entity driving_var is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic;
v : out std_logic
);
end driving_var;

architecture demo of driving_var is
begin
comb : process (a, b) is
variable v_v : std_logic;
begin -- process comb
v_v := a or b;
v <= v_v;
y <= a and v_v;
end process comb;
end architecture demo;

This adds clarity to the logic
and always works for synthesis.

Last I tested leo, 'driving_value
compiles ok, but the synthesis is
incorrect.


-- Mike Treseler


Peter Hermansson 11-26-2003 08:31 AM

Re: 'driving_value attribute
 
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bq081t$iv2$1$8300dec7@news.demon.co.uk>...
> "Peter Hermansson" <peter.hermansson@sts.saab.se> wrote in
> message news:4fc631bb.0311250405.1c94755b@posting.google.c om...
>
> > I have no luck in using the 'driving_value attribute. The following
> > simple code creates a "No driver in this region for 'driving or
> > 'driving_value attribute of signal v" error message in Modelsim.

>
> [...]
> > Architecture RTL Of test Is
> > Begin
> > v <= a or b;
> > y <= a and v'driving_value;
> > End Architecture RTL;

>
> > Have I misunderstood how to use this attribute?

>
> Yes, I think so. You have created two distinct
> processes: one for the assignment to v, one for
> the assignment to y. 'driving_value applies only
> inside a process, where it provides visibility of
> the value that THE CURRENT PROCESS is driving
> on to the chosen signal.
>
> What are you trying to do? I don't really see
> what meaning you ascribe to v'driving_value in
> the above code.
> --
>
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573 Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.



My intention was to read the value of the signal "v" sent out from the
entity, without using a "dummy" signal.

Regards, Peter


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