Does anybody use System Generator for DSP ?
Hi, I'm an Electronic Engineering student and I'm doing my Thesis using
System Generator for DSP v3.1 service pack 1.
I've done my model in Simulink and tested that it works. Later I generate
the netlist wihtout problems but when I try to synthesize in ISE 5.1 usin
the XST VHDL desing flow lots of warnings appear.
Above all this warnings;
WARNING:Xst:37 - Unknown property "syn_black_box".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
And many others like signals asigned but never used.
Why is the reason this warning appear? What should I do? Anybody could help
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