predefined function/library
 

Hello,

I tried to compile a vhdl file containing the function
addum(std_logic_vector,std_logic_vector)
Which library contain this function ?

thanks,

Vincent

Re: predefined function/library
 

Vincent,

I know the function addum (ADD Unsigned Magnitued) from the Viewlogic
environment in the past.
If your design includes types like VLBIT, VLBIT_1D, indeed ViewLog BIT, you
probably need a package with the name pack1076.vhd to compile it in a VHDL
complaint environment.

With a google for "pack1976.vhd" I found this location
(http://www.inst.bnl.gov/~jack/htmls/behv/)
Be sure that NOT to use VHDL-1993 but use VHDL-1987. (This package is
already very old!).

This function addum used vlbit_1d (not std_logic_vector). It can be that
someone has used the same name but for type std_logic-vector.

Success,

Egbert Molenkamp

"Vincent" <vincent.bruyerenospam@nospam.enst-bretagne.fr> wrote in message
news:bjfrum$uur$1@news-reader3.wanadoo.fr...
> Hello,
>
> I tried to compile a vhdl file containing the function
> addum(std_logic_vector,std_logic_vector)
> Which library contain this function ?
>
> thanks,
>
> Vincent
>
>

Re: predefined function/library
 

yes it is exactly what you mean !
it is used with types vlbit, vlbit_1d, ...
but it was said in the readme file it may be replaced by std_logic
so i replaced vlbit -> std_logic
vlbit_1d -> std_logic_vector
v1d2int( -> to_integer(unsigned(.
(the design is quite short, it is to design a PIC core)

but for the function, which one may i use to remplace addum, with the
std_logic library ?

Furthermore, i don't know if it was for the ViewLogic library but the
program use the following library :
-- library synth;
-- use synth.stdsynth.ALL;
i deleted it, is it useful ?

Thanks,

Vincent

"Egbert Molenkamp" <molenkam_remove_spam@cs.utwente.nl> a écrit dans le
message de news: bjhc6m$192$1@ares.cs.utwente.nl...
> Vincent,
>
> I know the function addum (ADD Unsigned Magnitued) from the Viewlogic
> environment in the past.
> If your design includes types like VLBIT, VLBIT_1D, indeed ViewLog BIT,
you
> probably need a package with the name pack1076.vhd to compile it in a
VHDL
> complaint environment.
>
> With a google for "pack1976.vhd" I found this location
> (http://www.inst.bnl.gov/~jack/htmls/behv/)
> Be sure that NOT to use VHDL-1993 but use VHDL-1987. (This package is
> already very old!).
>
> This function addum used vlbit_1d (not std_logic_vector). It can be that
> someone has used the same name but for type std_logic-vector.
>
> Success,
>
> Egbert Molenkamp
>
> "Vincent" <vincent.bruyerenospam@nospam.enst-bretagne.fr> wrote in message
> news:bjfrum$uur$1@news-reader3.wanadoo.fr...
> > Hello,
> >
> > I tried to compile a vhdl file containing the function
> > addum(std_logic_vector,std_logic_vector)
> > Which library contain this function ?
> >
> > thanks,
> >
> > Vincent
> >
> >
>
>

Re: predefined function/library
 

"Vincent" <vincent.bruyerenospam@nospam.enst-bretagne.fr> schreef in bericht
news:bjicsp$aa2$1@news-reader4.wanadoo.fr...
> yes it is exactly what you mean !
> it is used with types vlbit, vlbit_1d, ...
> but it was said in the readme file it may be replaced by std_logic
> so i replaced vlbit -> std_logic
> vlbit_1d -> std_logic_vector
> v1d2int( -> to_integer(unsigned(.

At that time, ~1990, most CAE tools had their own logical type. The VHDL
standard had type BIT and the users also wanted tri-state etc.
VLBIT is a four value logic ('X','0','1','Z'). It maybe that you can do the
suggetsed transformation in the package pack1076.vhd but I guess a synthesis
nowadays does not recognize that ADDUM is addition and will produce to
much/slow logic?

> (the design is quite short, it is to design a PIC core)
>
> but for the function, which one may i use to remplace addum, with the
> std_logic library ?

Since it is short design would indeed consider change it in std_logic.
It is already clear that ADDUM performs an unsigned addition. So if the
vectors are added the shortes vector is zero-exented (the function ADD2C
performs a signed addition, in this the shortest vector in sign extended).
If you change your design I would suggest using the IEEE package NUMERIC_STD
(based on std_logic) (USE IEEE.NUMERIC_STD.ALL).
E.g.
variable a : unsigned (3 downto 0);
variable b,c : unsigned (5 downto 0);

c := a +b; performs the unsigned addition (due to the type 'unsigned').

Ok. the is the solution HOWEVER wait a moment .. If you add two vector you
may need an extra bit for the result! The function ADDUM generates a result
that is 1 bit longer then the longest vector (.e.g. in contrast to the "+"
form the package NUMERIC_STD (or STD_LOGIC_ARITH) ).
variable a : unsigned (3 downto 0);
variable b : unsigned (5 downto 0);
variable c : unsigned (6 downto 0);

c := ('0'&b) + a; -- behaviour of addum; extend the longest vector with
'0'.

However I remember that in most designs the extra bit was not needed. So
addum 'generated' it, and the user removed the extra bit. So maybe you can
simple perform an addition.

>
> Furthermore, i don't know if it was for the ViewLogic library but the
> program use the following library :
> -- library synth;
> -- use synth.stdsynth.ALL;
> i deleted it, is it useful ?
>

Yes .. at that time. When I remember ViewLogic's synthesis tool needed it.
But indeed you can delete it now.

Egbert Molenkamp