Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   Delay of control signals (http://www.velocityreviews.com/forums/t21553-delay-of-control-signals.html)

Ingmar Seifert 08-18-2003 03:21 PM

Delay of control signals
 
Hello,

As desribed some threads above I have a multplier an adder and a
registerbank in a row.
I furtermore have a FSM that generates controlsignals for the
operand-multiplexers of each unit.

To control one run through this row I have to set the mul-control-signal
at first, one clock later the add-control-signal and two clock cycles
later the control-signal that chooses the location to store the result
of the run.

At the moment I set in state1 the mul-control-signal in state2 the
add-control-signal and in state3 the capture-control-signal.

Is it a common way to set all control-signals in one state and delay
them (with D-FlipFlops) by one and two clock cycles?



Thanks in advance.
Ingmar Seifert



All times are GMT. The time now is 04:13 AM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.