"William Wallace" <firstname.lastname@example.org> wrote in message
> 1. Is there a general rule I can use to know when I need to use the
> word "is" and when I do not? Also, what good does making somebody
> type these two characters do?
It means, for example, that the syntax doesn't need parentheses
around the selector of a "case" statement, because "is" acts as
a separator between the selector and the rest of the statement.
> 2. Is there a general rule I can use to figure out when two words are
> combined into one word (e.g., "elsif") versus being kept as two words
> (e.g., "end if")?
Yup. The only such elision in VHDL is "elsif" (a slightly mysterious
spelling; "elif" or "elseif" would perhaps have made more sense).
Contrast with Verilog's absurd statement bracketing syntax, with
the huge collection of elided terminators (endmodule, endcase,
endgenerate... and a scad more of them in SystemVerilog) and
interminable repetition of "begin...end".
> 3. Is there a general rule I can use to figure out when I need to put
> a semicolon (e.g., after the generic section and also the port section
> in the component declaration) and when I do not (e.g., not after the
> generic section but only after a port section of an instantiation)?
I agree this is fidgety syntax. Semicolon acts as:
- a statement TERMINATOR (one after every statement or declaration)
- a list SEPARATOR (one after every port specification in an
entity, except after the last one)
The second of these is likely to be regularised in VHDL-200x,
so that you can use semicolon at the very end of a port list if
As for the instantiation syntax, surely it makes sense that
the port and generic lists of an entity are quite separate
things, but the port and entity bindings on an instance
are part of the same statement?
> 4. Why if I pass a argument, say a std_logic_vector, to a function
> that takes a std_logic_vector, do I need to use data_in(arg'low) in
> the function as opposed to data_in(0). Why doesn't VHDL automatically
> rejustify a function call, say, function(data(15 downto 8)) to
> data_in(7 downto 0) in the function automatically?
So you can find out what you were given. If you want to renormalise
the input vector, you can easily do that using alias, constant or
function f (a: in std_logic_vector) return stuff is
constant norm_a: std_logic_vector(a'LENGTH-1 downto 0) := a;
This is one of several areas where VHDL has immense superiority
over Verilog. See my recently posted fixed-point arithmetic
package for a more extended example.
> 5. Is there a better way to bit reverse a bus than "new_bus(7 downto
> 0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
> hands cramps for large busses.
Yup; use a for loop or a generate loop, depending on the situation.
Unlike Verilog, you can do it in a completely general way, thanks to
exactly the thing you were complaining about with the function
arguments. (Needs VHDL-93 for the "reverse_range" attribute;
without that, a bit more work is required but it's still easy.)
There is an appealing recursive formulation too, also impossible
in Verilog, but this version is more practical.
function reverse_any_bus (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
for i in aa'RANGE loop
result(i) := aa(i);
end; -- function reverse_any_bus
Show me how to do that in Verilog :-)
> 6. What advantage is there in not allowing an port output to not be
> used on the rhs of an assignment in a module, forcing the RTL authors
> to create internal versions of such signals (e.g., "signal oData_v
> std_logic_vector(3 downto 0);") and later doing an assignment such as
> "oData <= oData_v;"?
It gives better consistency between entities and subprograms, but
I agree that it's a bit of a nuisance. On the other hand, creating
an internal signal is hardly a five-star headache.
> I have actually seen RTL code from VHDL
> engineers who did not know Verilog come up with even more ludicrous
> ways of solving this problem (routing an output back into a module as
> an input for use on the RHS of assigments inside the module).
There are people writing execrably bad VHDL, just as there are people
writing execrably bad Verilog. That's life.
> I have concluded that the people who came up with VHDL syntax were not
> working with each other, not referring back to previous decisions they
> made when making new ones,
Hmm. Maybe that's why the VHDL LRM is half the thickness of the Verilog
LRM, but is considerably more precise and consistent.
> and/or took the concept of "strongly typed"
> to a ludicrous extreme.
You mean, like, they chose to USE that concept? There's plenty that
needs fixing about VHDL, but very little of it is stuff that the
Verilog camp are likely to be able to teach us!
> It is also my belief that if it weren't for the government mandate,
> and the hordes of VHDL-only engineers these mandates created (VHDL
> fanatics who refuse to learn a better HDL), VHDL would be dead.
Believe away. You have many supporters.
> Any VHDL apologists care to explain?
I prefer to think of myself as an "HDL apologist", as someone who's
been using both Verilog and VHDL for a decade and who is very aware
that both have their considerable strengths and weaknesses.
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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