Re: problem in different clock speed when reading and writing from ram
You need to generate a signal from the 10 MHz domain that is long
enough for the logic in the uart clock domain to capture. A rule of
thumb for two totally asynchronous clocks is that it must be at least
two of the destination clock cycles in length. What you do then is
synchronize the signal in the target clock domain and then edge-detect.
The edge-detection pulse is the signal to the UART to start.
A possible implementation:
process (clk_10, reset_10) is
if (reset_10 = '1') then
toggle <= '0';
elseif (clk_10'event and clk_10='1') then
if (start_tx = '1') then
toggle <= not toggle;
process (clk_uart, reset_uart) is
if (reset_uart = '1') then
toggle_meta <= '0';
toggle_sync <= '0';
toggle_delay <= '0';
uart_start_tx <= '0';
elseif (clk_uart'event and clk_uart='1') then
toggle_meta <= toggle; -- metastable
toggle_sync <= toggle_meta; -- synchronized
toggle_delay <= toggle_sync; -- delayed
uart_start_tx <= toggle_sync xor toggle_delay; -- edge
Then uart_start_tx can be used by the UART logic.
In article <firstname.lastname@example.org> , sarah
> I have a clock problem when implementing reading and wrting data from
> ram in FPGA.
> First, write data to ram. The write clock is 10 Mhz. Then after
> finishing writing, read data from ram and send them to UART. The
> problem is here, the reading clock is the same as UART_clock, much
> slower than 10 Mhz. In the UART, the transmitter block is controlled
> by the signal: start_tx. It means when start_Tx is '1', the data can
> be trasmitted. But this signal is triggered by the high speed clock,
> 10 mhz. The transmitter block can work under the uart-clock. So, i
> need to keep the signal : start_tx longer until the rising endge of
> Does anyboday know how to slove this problem? Which logic should be
> Thank you very much.
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