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Willem Oosthuizen 07-09-2003 10:19 AM

Re: Multi-dimentional arrays in components using generics
 
I can put the types in a PACKAGE, but how do I pass the generics to the
PACKAGE?

"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:begood$1u5$1@ctb-nnrp2.saix.net...
> How do I do multi-dimentional arrays in components using generics
>
> I tried the following. This does not work. I need to define the type
> array(Depth -1 downto 0) of std_logic_vector(Width-1 downto 0) and
> type array(Depth -2 downto 0) of std_logic_vector(Width-2 downto 0)
> somewhere. But where?
>
> COMPONENT Reduce is
> generic
> ( Width : integer;
> Depth : integer
> );
> port
> ( D_IN : IN array(Depth -1 downto 0) of std_logic_vector(Width-1 downto
> 0);
> Q : OUT array(Depth -2 downto 0) of std_logic_vector(Width-2

downto
> 0);
> );
> end COMPONENT;
>
>
>
>




Jonathan Bromley 07-09-2003 12:13 PM

Re: Multi-dimentional arrays in components using generics
 
Hi Willem,

> "Willem Oosthuizen" <willy@asic.co.za> wrote in message
> news:begood$1u5$1@ctb-nnrp2.saix.net...
> > How do I do multi-dimentional arrays in components using generics
> >
> > I tried the following. This does not work. I need to define the type
> > array(Depth -1 downto 0) of std_logic_vector(Width-1 downto 0) and
> > type array(Depth -2 downto 0) of std_logic_vector(Width-2 downto 0)
> > somewhere. But where?

[and then...]
> I can put the types in a PACKAGE, but how do I pass the generics to the
> PACKAGE?


This is all a bit horrible in VHDL. When you make an array of something,
the full details of that "something" must be known. Your need for a
parameterisable 2-dimensional array is usually solved in one of the
following ways:

(1) Use a true 2-dimensional array
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

type Arr2D is array (Depth-1 downto 0, Width-1 downto 0) of std_logic;

This is legal VHDL, and you can then create arrays and subscript them:

signal S: Arr2D;
....
S(3,4) <= '0';

But unfortunately it doesn't play well with std_logic_vector
because there is no easy way to copy a row or column of this 2-d
array to/from a 1-D vector - you have to use a FOR loop.

(2) Put the subtype in a package
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

as you suggested...

package MyTypes is
constant Width: integer; --- deferred constant, no value
subtype Row_T is std_logic_vector(Width-1 downto 0);
end;

....
type Vec2D is array(Depth-1 downto 0) of Row_T;

But then, as you say, you need "to pass a generic
into the package". You can't do that. There is only
one "instance" of a package in any given VHDL simulation,
so the package can't have a generic. I've got close to
what you need by using a deferred constant; you set
up the deferred constant's value in the package body:

package body MyTypes is
constant Width: integer := 5;
end;

This package body can be compiled separately, just before
you elaborate the design, but the same Width value will apply
throughout the simulation.

(3) Fake it up with a big 1-D array
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

No help at all, because you can't take a slice
that has non-static bounds.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Sorry I can't help more. It's a somewhat messy problem.




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