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-   -   unused bits in signals (http://www.velocityreviews.com/forums/t21392-unused-bits-in-signals.html)

Thomas 07-05-2003 11:47 PM

unused bits in signals
 
I have to talk to registers that are 8 bits, but some bits are totally
unsused in them;

I get tons of warning from the synthetizer, using Xilinx's tools

for example:

signal myregister : std_logic_vector(7 downto 0);

but I am only using bit 2 and 3, but I need to have it 'formatted' over 8
bits so that I can do: myregister <= my8bitdata and it ignores everything
but the bits 2 and 3?

in short I am trying to find a way to tell the tool: I care only about
these bits, don't warn me about the others, I know I'm not using them.


Mario Trams 07-06-2003 09:05 AM

Re: unused bits in signals
 
Thomas wrote:

> I have to talk to registers that are 8 bits, but some bits are totally
> unsused in them;
>
> I get tons of warning from the synthetizer, using Xilinx's tools
>
> for example:
>
> signal myregister : std_logic_vector(7 downto 0);
>
> but I am only using bit 2 and 3, but I need to have it 'formatted' over 8
> bits so that I can do: myregister <= my8bitdata and it ignores everything
> but the bits 2 and 3?


Why not using

signal myregister: std_logic_vector(3 downto 2);
....
myregister <= my8bitdata(3 downto 2);

???

Regards,
Mario

--
----------------------------------------------------------------------
Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------

Mario Trams 07-06-2003 10:22 PM

Re: unused bits in signals
 
Thomas wrote:

>> Why not using
>>
>> signal myregister: std_logic_vector(3 downto 2);

>
> I didn't realize you could do that!; for some reason, I was assuming that
> things had to either start or end at 0; that's going to help, I have so
> many warnings all over the place; is there a syntax to do something like
> that : std_logic_vector(5 downto 4, 2 downto 1) /


I've never used it and I have never heard about it.
Check some documentation!

Regards,
Mario

--
----------------------------------------------------------------------
Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------


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