VHDL SIGNED datatype
 

Hi,

I am a newcomer to VHDL and the Xilinx ISE. I have no previous
experience and my knowledge of the ISE and VHDL are rather low :(. I
needed to use the 16pt. IFFT core and so I used the CORE Generator to
generate it. Now the problem is that the core expects 2's complemented
inputs and outputs in the form of STD_LOGIC_VECTOR. I had a look at
the VHDL datatypes and saw that the SIGNED type is suitable for 2s
complement representations .. now I am really confused about all these
and have no clue what to do .. I tried changing the
std_logic_vector(a:b) lines to SIGNED(a:b) but the compiler gives me a
warning that only std_logic and std_logic_vector types are available.
I have included the library line "use IEEE.STD_LOGIC_ARITH.ALL".

Can someone please tell me how to get around this??

Actually the main problem I have is with the 2s complement
representation of signed real numbers .. as long as my output values
are integers it's OK .. but when I have fractional outputs I get a '1'
if the number is positive, and a '0' if the number is a negative
fraction. so far I only got it to work for values like 1,-1,and,0.

Re: VHDL SIGNED datatype
 

darkknight_9@hotmail.com (Mostafa) wrote in message news:<c791dcd4.0307010852.187936b8@posting.google. com>...
> Hi,
>
> I am a newcomer to VHDL and the Xilinx ISE. I have no previous
> experience and my knowledge of the ISE and VHDL are rather low :(. I
> needed to use the 16pt. IFFT core and so I used the CORE Generator to
> generate it. Now the problem is that the core expects 2's complemented
> inputs and outputs in the form of STD_LOGIC_VECTOR. I had a look at
> the VHDL datatypes and saw that the SIGNED type is suitable for 2s
> complement representations .. now I am really confused about all these
> and have no clue what to do .. I tried changing the
> std_logic_vector(a:b) lines to SIGNED(a:b) but the compiler gives me a
> warning that only std_logic and std_logic_vector types are available.
> I have included the library line "use IEEE.STD_LOGIC_ARITH.ALL".
>
> Can someone please tell me how to get around this??
>
> Actually the main problem I have is with the 2s complement
> representation of signed real numbers .. as long as my output values
> are integers it's OK .. but when I have fractional outputs I get a '1'
> if the number is positive, and a '0' if the number is a negative
> fraction. so far I only got it to work for values like 1,-1,and,0.


Hi Mostafa,
Most of the simulators support 2's complement arithmetic using
std_logic_vector. Alot of companies have ported some orignal packages
created by synopsys call std_logic_unsigned and std_logic_signed to
there tools so that you can use 2's complement arithmetic on std_logic
type.
I would suggest that you look to see what the name of the library
is it is usually called std_logic_signed. So you would need to add
the "use ieee.std_logic_signed.all" to the library line. Then you can
do 2's complement math using std_logic.

You can represent any number between -2^n to (2^n)-1 using two's
complement. The fractional bits are all based on interpertation of
the number. Basically you put a decimal point at a fixed location and
then you can interpert the bits to the right of the decimal points as
fractional bits and bits to the left as integer bits. A better
explanation of fixed point math is located at :
http://personal.bellsouth.net/y/a/yatesc/fp.pdf

jon

Re: VHDL SIGNED datatype
 

Dear Jon,

Thanks a lot for your reply. I shall read though the PDF and see if
that helps. In the mean while, if you have the time and the tools,
could you please have a look at the project ? Right now it's nothing
more than just the core and a testbench for it:

http://325720.tripod.com/vhdl/

The project is a self-extracting RAR archive and it was created using
Xilinx ISE 5.1i, HDL Bencher, and ModelSim to simulate.

I really appreciate the help.

Thanks again,
- Mostafa

Re: VHDL SIGNED datatype
 

Hello Jon,

I have read the article but I'm not sure how much of a help that is
... The reason is that I do not have any knowledge about the number of
bits to allocate for the integer part and the fractional part. Besides
the output that I get out of the block does not resemble any kind of
2s complemented signed rational number. Here is an example of what I'm
talking about:

using MATLAB:

>> tmp(2,1) =-20i
tmp =
1 + 1i
0 - 20i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
1 + 1i
>> ifft(tmp)
ans =
0.9375 - 0.3125i
0.44453 - 1.2365i
0.88388 - 0.97227i
1.1887 - 0.56001i
1.3125 - 0.0625i
1.2365 + 0.44453i
0.97227 + 0.88388i
0.56001 + 1.1887i
0.0625 + 1.3125i
-0.44453 + 1.2365i
-0.88388 + 0.97227i
-1.1887 + 0.56001i
-1.3125 + 0.0625i
-1.2365 - 0.44453i
-0.97227 - 0.88388i
-0.56001 - 1.1887i

Now, simulating this with ModelSim using a testbench created with HDL
Bencher:

The testbench file can be found here: http://325720.tripod.com/vhdl/

The input test vectors therefore were:

Real_Input Imag_Input
---------------- ----------------
0000000000000001 0000000000000001
0000000000000001 1111111100111000
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001
0000000000000001 0000000000000001

But the output generated by the simulator was:

Real_Output Imag_Output
---------------- ----------------
0000000000000000 1111111111110101
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100
1111111111111111 1111111111110100


All except the first are the same. Looking at the output from MATLAB I
would expect all 16 components to have at least differing binary
values but this is obviously not the case.

Any idea what I'm doing wrong?

- Mostafa

Re: VHDL SIGNED datatype
 

Hi Jon!


>>Now the problem is that the core expects 2's complemented
>>inputs and outputs in the form of STD_LOGIC_VECTOR. I had a look at
>>the VHDL datatypes and saw that the SIGNED type is suitable for 2s
>>complement representations .. now I am really confused about all these
>>and have no clue what to do .. I tried changing the
>>std_logic_vector(a:b) lines to SIGNED(a:b) but the compiler gives me a
>>warning that only std_logic and std_logic_vector types are available.
>>I have included the library line "use IEEE.STD_LOGIC_ARITH.ALL".


> Most of the simulators support 2's complement arithmetic using
> std_logic_vector.

.... depending on the included packages.

> Alot of companies have ported some orignal packages
> created by synopsys call std_logic_unsigned and std_logic_signed to
> there tools so that you can use 2's complement arithmetic on std_logic
> type.

It's not recommended to use this packages, because they are implemented
different on different systems. You may have one version included with
your simulator and an other with your synthesis tool. Use
IEEE.numeric.std.ALL instead.

Furthermore: If you want to subtract two std_(U)logic_vectors, how
should the simulator know if you use two signed (2's complement) or
unsigned values? -> Because of this data types signed and unsigned exist.



May way: Evertimy I need to do some arithmetic operations, I convert my
data - e.g. (code fragments):

Use IEEE.numeric.std.ALL

signal result,a,b : std_ulogic_vector(x downto 0);

result <= std_ulogic_vector( signed(a) - signed(b) );



Normally one does not need often arithmetic operations, so the coding
overhead is _very_ low.

Ralf

Re: VHDL SIGNED datatype
 

Oh well .. All problems solved as far as I am concerned :) .. it seems
that all I had to do was to scale the data into a much wider range so
that the decimal point gets pushed far to the right and I end up
dealing with numbers with a large integer part. Thanks a lot to all
again for the replies.

FFT core
 

As'salaam alaykom Mostafa,

can you help me please create an fft core from core generator as I have been trying and each time I try to simulate I get zero results, I'd appreciate your help really as I am newbie to VHDL.

thanks in advance,
Hussain