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  1. Distributed Ram with Initial Values (Virtex)
  2. signal ram: ram_t := (others => (others '0'));
  3. Ask about finding maximum and second's maximum number in array is given.
  4. Chasing Bugs in the Fog
  5. How can I avoid variable in this loop (outside the process)?
  6. Cannot find function "TO_INTEGER" for these actuals
  7. [ANN] LOOPGEN-Fast hardware looping VHDL IPs
  8. DSP48 in synchronous process or not, what's the difference?
  9. vmkr segmentation fault
  10. ram problem
  11. Synchronous programmable counter
  12. How do measure Power,Delay and area in vhdl
  13. 2 counters, counting states of Bit stream
  14. HELP! VHDL real TYPE produces infinite decimal. How to approximateor reduce precision?
  15. get accustomed with vhdl 2008
  16. A few question about vhdl(clk,signal,etc..)
  17. vhdl-mode emacs - what does creating a Project do?
  18. Calculating Pulse per minute in a FPGA
  19. train ticket machine help needed!
  20. Cascading the attributes
  21. implementation of traffic light...
  22. abstract type signal
  23. Signal xx cannot be synthesized, bad synchronous description error
  24. Displaying a 4-digit integer number on 7-segments
  25. Asynchronous With Select and When Else Statements
  26. Counting number of asserted register bits in VHDL
  27. Generics, packages, and VHDL-2008
  28. VHDL Standards Invitation and Status
  29. verification strategy with no specs
  30. VHDL Model for a MIPS Processor
  31. help for usb3300
  32. clocked process and sensitivity list
  33. Announcing release of OSVVM 2013.04
  34. write(output, string)
  35. Re: Application for a job of design engineer
  36. conv_integer
  37. Design entry poll: which is your favorite editor?
  38. Re: Compiler Question
  39. CFP - High-level synthesis - Methodologies and Practice
  40. Compiling error... not sure how to address the errors
  41. Dual Edged Counter
  42. Convert ADC output format to DAC input
  43. need vhdl code for 8 bit simple cpu
  44. VHDL code PROBLEM ,how to create shift left operation withoutregister in vhdl
  45. Hexadecimal value (literal) as function parameter, is it possible?
  46. configurable number of interfaces
  47. Definition Multiply and Division in VHDL
  48. mutliple input through same input lines
  49. Which function takes precedence when multiple are visible?
  50. Architecture name through hierarchy
  51. image compression using golomb-rice algorithm
  52. precedence of a downto clause
  53. Digital Counter Error
  54. "Non-static aggregate with multiple choices has non-static otherschoice."
  55. Feedback loop in VHDL-AMS
  56. Clock Switching in VHDL/ Actel igloo nano device
  57. Conditional Assignments in Constants
  58. Mathematical formula implementation
  59. System Verilog
  60. Memory Mapped Register Help
  61. Data type conversion
  62. VHDL code verification
  63. AMBA AHB COMPLAINT MEMORY CONTROLLER
  64. Re: MP3 encoder
  65. Resolved vs. Unresolved standard logic, and when to get away with using each
  66. Hardware Acceleration VGA graphics controller
  67. Is this kind of writing useful?
  68. Immunizing Design/Simulation From Unknowns
  69. Set std_logic_vector values in a range
  70. ethernet on spartan 3an
  71. What is the difference of "array (63 downto 0) of ...." and "array (0to 63) of ...."
  72. VHDL-AMS: Simulating a closed model in Mentor Graphics System Vision
  73. Why does Modelsim not display some signals?
  74. Assign a value to a position in a std_logic_vector
  75. Does the last elseif run or not?
  76. Free PDF Combinational Logic book download that introduces Quartus II
  77. to_unsigned as an expression in an aggregate
  78. Why ever use std_logic_vector intead of signed/unsigned?
  79. For verification, what's the best way to introduce delay offsetbetween a DUT's data array?
  80. compilation errors with no clues(modelsim)
  81. Scott Cooper's book on VHDL-AMS
  82. concurrent assertion statement and delta races
  83. Emacs VHDL-mode Next-Error, Previous-Error, and First-Error are not working...?
  84. VHDL-2008 Reference Book
  85. VHDL-2008 videos on Verification Academy
  86. Vhdl syntax for generate ...
  87. Emacs, VHDL Mode - Upper Case Enum Values & Upper Case Constants (not working)?
  88. Sometimes I Just Don't Get the Tools
  89. What is a signal?
  90. Error (10028): Can't resolve multiple constant drivers for net"light" at LED.vhd(25) NEED HELP!
  91. the most beautiful\valuable vhdl-projects (categorized)
  92. noob question on loops
  93. assignment constraint check time
  94. What is the base type?
  95. exponential function
  96. help in writing code for modified booths radix4 algorithm using
  97. Re: multiplier
  98. Can an out port be set to Hi-Z
  99. VGA controller
  100. Lattice iCECube2 for iCE40 Devices
  101. Initial execution of the processes and sensitivity list
  102. time to digital convertor
  103. Function for direct conversion integer > slv
  104. Unresolved reference message
  105. Syntax for conversion functions on inout ports
  106. important vhdl code for speech recognition
  107. Matrix multiplication
  108. Type declaration in package
  109. procedure problem
  110. DAC5672 distorted sine out
  111. entity parameterization
  112. What does 'SnKDone' signal stand for?
  113. VHDL expert puzzle
  114. Emacs, makefile and Aldec Riviera-Pro
  115. 8bits to 7segments bcd decoder
  116. signal AND with a constant of '1'
  117. 2 digit dice (random counter 1 - 6)
  118. Why on Simulation the result is not what is expected?
  119. Want to add signal timing waveforms in VHDL comments (any tools out there?)
  120. Time Divided by Time is What?
  121. Sting Signal into Vcd file
  122. defines both a type and a subtype
  123. Generating a 78MHz clock from a 100MHz base clock (VHDL)
  124. Generating a 78MHz clock from a 100MHz base clock
  125. Verilog Counter Question
  126. vhdl guessing game
  127. Can we log internal signals from a testbench in VHDL?
  128. search some good vhdl preprocessor (opensource)
  129. VHDL CODE FOR CONTROLLER WHEN PLANE IS DESIGNED USING THREE POINTS
  130. how to implement reed solomon encoder on fpga spartan 3e kit
  131. Hierarchical References out of generate block
  132. Is there a way to make testbenches assume simulation failure as default?
  133. What does this Verilog code do?
  134. verilog
  135. vhdl code for 8-bit galois field multiplication
  136. any simple way to load test vector in testbench that contains decimal format?
  137. Methods for flow control
  138. function printf in VHDL
  139. finite state machine- bad synch description
  140. doing sqrt( ) for synthesis.
  141. SLV reverse bit order
  142. Bidirectional bus connection
  143. Pipelining a large mathematical equation
  144. Concatenate/De-Concatenate
  145. Overflow on INTEGER value.
  146. Why a signal cannot control the file IO operation?
  147. internal signal delay problem
  148. FPGA - Offset in/out values
  149. operator vs. function
  150. fastest complex division algorithm
  151. VHDL programming
  152. Querying Active-HDL from TCL
  153. newbie with timing problem, is adding pipeline stages the only optionto speed up?
  154. how to start post synthesis simulation
  155. negative slack
  156. change variable in case statement
  157. change variable in case statement
  158. The International Conference on Computing, Networking and DigitalTechnologies (ICCNDT2012)
  159. Re: Why not mix concurrent and synchronous assignments in the same process?
  160. Problem with Comments in Emacs (want them to stop aligning)
  161. clk event at firs simulation cycle
  162. Re: Why not mix concurrent and synchronous assignments in the same process?
  163. vhdl-gui experience
  164. intialisation of matrix of integers
  165. inout pin problem
  166. "Open" banned on procedures - Is this an LRM thing?
  167. END OF DATA ON A FRAME
  168. help for end of data
  169. Modelsim Problem
  170. Ko counter in Test Bench
  171. 1200 baud rate generator
  172. comparing characters from strings
  173. attribute signal name in procedure
  174. use vhdl program in matlab
  175. how can I drive an array from a component to the top level ??
  176. how to duplicate a component
  177. Re: VHDL Help
  178. State machine definitions
  179. Re: VHDL Help
  180. how to define a type with inputs and outputs like a bus
  181. Exporting a constant from component to it's parent
  182. signal and variable assignment problems
  183. alias: variable is an object but is not an object
  184. read binary file
  185. Probelm with modelsim.ini
  186. procedure call name vs.association_list ambiguity
  187. Unsupported clock statement error !!!
  188. Mixing different VHDL revisions between package and entity
  189. help with an error
  190. What about a new attribute to access the physical representation of a signal ?
  191. The definition of combinatorial process?
  192. Modelsim MXE on wine?
  193. A cheap or free version of VHDL?
  194. A cheap or free version of VHDL?
  195. What closes the implicitly open file?
  196. Call for beta users for Sigasi integration with Altera Quartus
  197. help needed regarding VHDL, GHDL and gtkwave
  198. wait for, vhdl
  199. Check all bits set
  200. Flipflops
  201. Counter defined as "integer range 0 to X"
  202. bcd-7segment decoder
  203. character to string
  204. File write of time & date
  205. Using numeric_std packages
  206. Help with instruction fetch unit in VHDL
  207. multiple individual bidirectional signal concatenated into 1bidirectional bus
  208. GHDL problems with (apparently) valid "alias"
  209. unsigned + std_logic
  210. divider algorithm
  211. Announcement: Sigasi integrates with Aldec compiler
  212. Types of bits
  213. Generic for port with array type
  214. sensitivity list in concurrent assertion
  215. vhdl IRC
  216. Tips for handling switch bounce?
  217. Coding timinig relationship
  218. Data conversion
  219. VHDL Type Mismatch error indexed name returns a value whose type does not match
  220. ERROR: Index name XXX is not static.
  221. Help with variables and 'for' loops
  222. case when <subtype> =>
  223. error in synthesis in vhdl code...
  224. dqpsk decoder
  225. signals VS variables
  226. Repeating Generate loop
  227. Re: Really Rusty in VHDL...
  228. Re: VHDL sound generator
  229. Shared variables and protected types
  230. bidirectional bus problem
  231. Re: Really Rusty in VHDL...
  232. Re: Really Rusty in VHDL...
  233. Is this a synthesizable code?
  234. Creating delay chain with generics
  235. VHDL ISA Bus Assignment Help
  236. Division
  237. VHDL automate help, beginner
  238. how to declare array???
  239. Behavior of VHDL comparison operator with integer argument
  240. State machine with D Flip Flop
  241. Ideas on higher level design
  242. Parametrized CLA adder in VHDL
  243. warning xst 2170
  244. Signed Arithmetic using VHDL Operators
  245. Problems switching to ieee.numeric_std.all
  246. waring in vhdl Xst:1355
  247. Counter with asynchronous enable
  248. Concatenate bits
  249. Concatenate bits
  250. modelsim error, help me