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  1. How to make this code generic?
  2. inside or outside of the case statement ?
  3. how to output clear signal
  4. 2002 buffer mode port support?
  5. How to access individual bits of std_logic_vector
  6. TimingAnalyzer -- Build Timing Diagrams directly from VHDL orVerilog
  7. Slice assignment problem - help requested
  8. dynamically accessed subrange of a vector
  9. switch to verilog module in a vhdl wrapper
  10. Configuration of instances
  11. question regarding modelsim - systemC testbench
  12. New tech competition
  13. vhdl testbench sequential
  14. How to extract subarray ?
  15. HPCS-10 Call for papers
  16. Continuous Queue in VHDL?
  17. error in simulation of floating point adder
  18. Alliance 5.0 stimulus file syntax error - Request help
  19. Four Bit Adder Help For ALU
  20. Question on "slack"
  21. Alu
  22. Why usign a Variable here won't work ?
  23. RS-232 or SPI
  24. FPGA Camp is tomorrow - 11/11 - silicon valley - Dinner provided
  25. [Announce] Jan on HDL Design
  26. ise synthesis error - use of null array on signal X is not supported
  27. Exporting data from ram
  28. WALK IN'S for jobs send resume
  29. got crazy about variable index...
  30. Question about Gaussian Noise Generator?
  31. SPAM levels
  32. generic
  33. Operator problem VHDL. Beginner
  34. Generic Comparator using VHDL
  35. Variable Read Before Assigned
  36. Quantization
  37. VHDL Beginner Help
  38. Problem populating a SLV using aggregates
  39. GTKWave not showing signals of user types
  40. Creating delay in divider
  41. how to output a 400hz sound from a xs 95 board using a 4 bit counter
  42. Generate Statement
  43. Selecting generic at simulation time.
  44. vhdl range in verilog
  45. need help on VHDL
  46. Any idea about double buffering
  47. Representing the buffer with logic gates,flipflops
  48. vhdl
  49. VHDL Programming? Parallel Counter?
  50. fpga IOB
  51. fpga clock resolution
  52. VHDL configuration
  53. vhdl testbench help
  54. how to convert real to std_logic
  55. need help with VHDL code ....ARRAY
  56. Hi Needed Urgently
  57. SPR
  58. Wait on statement
  59. VHDL documentation tool
  60. Idea to implement ring buffer
  61. SCLive 3.0 With Verilog, VHDL, SystemC kernels available.
  62. procedure as argument in procedure
  63. How to Input a matrix in VHDL
  64. simulating records
  65. Situations in which 'else' or 'elsif' are unnecessary.
  66. Synthesis wrapper
  67. write(L, bitout(0)); -> cool but where yer two arguments?
  68. transaction recording
  69. TEXTIO drives me crazy!
  70. Philosophical placement of counter
  71. How can we get rid of all the spam in this group?? Aren't there somekind of filters??
  72. Dynamic Power Consumption Estimates/Comparison
  73. a quick query!
  74. Re: mapping input/output port
  75. how to define frame structure?
  76. Announcing Nov'11 FPGACamp, Silicon Valley. "Debugging Your FPGA"
  77. hey ppl????
  78. How to make custom types visible in other .vhd modules
  79. "Library unit is not available in library work"
  80. sig : process vs. process(sig)
  81. RS232 help!
  82. #Error loading design
  83. GNU Lesser Public License and Soft IP
  84. vacancy's for fresh\exp apply resume
  85. Modelsim under 64-bit Linux
  86. simulink modelsim cosimulation
  87. hi frnds
  88. Any body can explain whats wrong with this simple code ERROR:Xst:827
  89. c(0) <= a(0) + a(1); Found 0 definitions for operator "+"
  90. Source code encryption
  91. △▲△wholesalw cap ed hardy cap coogi cap lv cap etc with factory price
  92. Synplicity tool
  93. External names vhdl2008
  94. [EN]&[IT] VHDL, memory hierarchy
  95. using multiple ranges
  96. Why use DSP builder over HDL?
  97. count until read next signal
  98. 2's compliment+parity+parallel to serial help please...
  99. VHDL for PCB design?
  100. Please recommand a VHDL book for synthesis purpose
  101. coregen help
  102. Signals too slow
  103. port initial value
  104. ↑〓↑○↓〓↓wholesalw cap ed hardy cap coogi cap lv cap etc with factory price
  105. How to implement a counter
  106. Re: Spam on comp.lang.vhdl
  107. Image Processing in VHDL
  108. multiplier
  109. Checksum comparisons
  110. why this forum not moderated?
  111. vhdl: wrong index type
  112. Re: Spam on comp.lang.vhdl
  113. Instantiating VHDL/Verilog modules (Generating the top level) usingan XML configuration file
  114. [VHDL] driver question
  115. clock divider quetion
  116. Stopping the simulation in Modelsim Altera Starter Edition/Linux?
  117. how to implement this c++ algorithm in vhdl
  118. Verification Question
  119. Generic Multiplexer
  120. vacancy's for hardware&networking jobs apply resume
  121. Testbench for geting currect time in ModelSim
  122. linking readable port names with indexed array
  123. Nike Shox Sneakers
  124. ∴∨∵∧∵wholesalw cap with factory price
  125. state machine help
  126. Writing a binary output file
  127. Newbie VHDL Blocks
  128. xilinx warning message
  129. clocked for loop with conditional if...
  130. ieee.math_real-support in Synplify for Lattice
  131. Re: How many bits?
  132. How many bits?
  133. Pointer clarification needed
  134. how 2 write vhdl for stepper motor
  135. How To Write Vhdl For Stepper Motor
  136. Mac OS X support for Sigasi HDT
  137. OT: Verizon will drop ALL newsgroups on 30 September
  138. ModelSim vs Aldec -- odd difference
  139. I'm looking for a review of Doulos VHDL courses
  140. Suggestion for Frame Handler Design
  141. classic NBA Jersey NFL Jersey korea supplier
  142. Does ModelSim or any simulator software have a function similar tothe standard function any logic analizer has?
  143. std_logic_vector to string in hex format
  144. SPI, I2C and CPLD
  145. Assigning entire row in a 2d array?
  146. Help in VHDL for Test becnh signal generation
  147. Bus Emulation in Testbenches
  148. Post-Synthesis simulation runs into iteration limit
  149. record of a record to std_logic_vector
  150. Accumulator type DCO
  151. Why there is multi-source error?
  152. CFP - Journal of Systems Architecture, Embedded Software Design(Elsevier), Special Issue on Hardware/Software Co-Design
  153. how to pass input values to procedure
  154. Template for programming devices
  155. coding style for arithmetic operations
  156. Resource/operator sharing, good or not?
  157. Entity Generics Question
  158. Multi-source
  159. Real Random Number Generator
  160. Encoder counter problem
  161. vhdl code for Manchester
  162. conversion code
  163. a small clarification please
  164. Manchester representation
  165. serial stream data to capture in parallel line
  166. IP Core Wizard-Demystified
  167. using FIFO in vhdl
  168. how 2 write vhdl for dsp applications
  169. Loops for write access
  170. VHDL Testbench representation
  171. Using carry chain of counters for term count detect
  172. Re: Mixed language simulation on the cheap
  173. what is difference between generate and for loop in vhdl
  174. new version TimingAnalyzer
  175. Re: Mixed language simulation on the cheap
  176. Re: Mixed language simulation on the cheap
  177. Re: Mixed language simulation on the cheap
  178. Re: Mixed language simulation on the cheap
  179. Nonlinear Time Scale ModelSim
  180. Array assignment
  181. A few VHDL questions
  182. FPGA-Camp - A mini conference on FPGAs, (Aug'26, Silicon Valley)
  183. The HDL Complexity Tool beta testing.
  184. Reading a Vector to Create 5/9 Smoother
  185. VHDL record synthesis
  186. gtkwave-3.2.2 released
  187. Re: 3state/gate-based MUXes
  188. Re: 3state/gate-based MUXes
  189. Help with frequency divider
  190. Connecting an inout port to another inout port
  191. Reading 16 bit words from a file
  192. Why cant protected types be elements in an array?
  193. Synplify - Init Rom from file - Howto?
  194. HELP! Searching for research participants
  195. AM 2901 VHDL microprocessor slice
  196. Syntheis report??
  197. EVERAGE
  198. Xilinx BRAM initialization with .coe file
  199. VHDL code in Latex
  200. read from a file
  201. 8bit register with ALU computation
  202. How to make Unconstrained std_logic_vector port :)
  203. Stumped in Simulation Land
  204. VHDL process and function problem
  205. signal assignment and Delta delay
  206. Altera VS Xilinx
  207. Difference between two process
  208. Multiplication of 1 bit with vector
  209. Naz - Computers and Laptops
  210. Natural Food For Long & Smooth Life Style..
  211. CPLD Algorithm
  212. Fir Question
  213. ADAPEX
  214. Is there a way to extract vhdl code from an fpga?
  215. Synthesis VS Simulation
  216. Provider of EDA tool licensing and MPW services in Singapore
  217. Provider of EDA tool licensing and MPW services in Singapore
  218. xilinx bram not connected?
  219. Do you prefer paper or plastic... er, I mean paper or e-books?
  220. Using OPEN in port map
  221. Some support for VHDL project
  222. HELP required floating point multiplier on FPGA
  223. Can I include include a constant in a constant array?
  224. Re: Random distribution in VHDL
  225. Array of bits on to a signal in VHDL
  226. testbench question
  227. latch problem
  228. Why self defined type signal cannot assign value multiple times?
  229. Constants?
  230. Back to the future
  231. std_logic_textio library
  232. Interpolation in VHDL
  233. syncronizer
  234. Breaking parallel multiplier into two pieces in VHDL?
  235. Dual_port_BRAM
  236. How can I access a 2d array completely.
  237. issue with Chipscope
  238. How to force an internal wire which is deep inside DUT hierachy attop level testbench using VHDL design?
  239. modelsim doesn't like my increment w/wraparound
  240. Simulating Inverted Registers
  241. BAUD rate problem
  242. NEXYS2 Board from Digilent
  243. Adding signals of different size
  244. I've got a case of the latches....
  245. Airlines
  246. Need help initializing LPM_Add_Sub to do Sub
  247. FPGA / CPLD Group on LinkedIn -- Networking Group
  248. Neil Nitin Mukesh:I weight-train four days a week and concentrate onone body part every day
  249. Expand unsigned 4*4 module to signed 16*16 module
  250. Re: pre-initialized dpram functional simulation