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  1. Target type ieee.std_logic_1164.std_ulogic in signal assignment isdifferent frim expression type std.standard.integer.
  2. Operator on array slice
  3. Re: Syntax question about aliases
  4. Re: discrepency between behavioral simulation and post routesimulation
  5. Re: Syntax question about aliases
  6. converting std_logic_vector to an integer without sign extension
  7. 10 Reasons Why YOU Should Join Us
  8. Capturing loop index some problems
  9. Record Creation in VHDL
  10. Length of Range
  11. Date Time Directory Project String
  12. FPGA + Ethernet
  13. How to make this code generic?
  14. inside or outside of the case statement ?
  15. how to output clear signal
  16. 2002 buffer mode port support?
  17. How to access individual bits of std_logic_vector
  18. TimingAnalyzer -- Build Timing Diagrams directly from VHDL orVerilog
  19. Slice assignment problem - help requested
  20. dynamically accessed subrange of a vector
  21. switch to verilog module in a vhdl wrapper
  22. Configuration of instances
  23. question regarding modelsim - systemC testbench
  24. New tech competition
  25. vhdl testbench sequential
  26. How to extract subarray ?
  27. HPCS-10 Call for papers
  28. Continuous Queue in VHDL?
  29. error in simulation of floating point adder
  30. Alliance 5.0 stimulus file syntax error - Request help
  31. Four Bit Adder Help For ALU
  32. Question on "slack"
  33. Alu
  34. Why usign a Variable here won't work ?
  35. RS-232 or SPI
  36. FPGA Camp is tomorrow - 11/11 - silicon valley - Dinner provided
  37. [Announce] Jan on HDL Design
  38. ise synthesis error - use of null array on signal X is not supported
  39. Exporting data from ram
  40. got crazy about variable index...
  41. Question about Gaussian Noise Generator?
  42. SPAM levels
  43. generic
  44. Operator problem VHDL. Beginner
  45. Generic Comparator using VHDL
  46. Variable Read Before Assigned
  47. Quantization
  48. VHDL Beginner Help
  49. Problem populating a SLV using aggregates
  50. GTKWave not showing signals of user types
  51. Creating delay in divider
  52. how to output a 400hz sound from a xs 95 board using a 4 bit counter
  53. Generate Statement
  54. Selecting generic at simulation time.
  55. vhdl range in verilog
  56. need help on VHDL
  57. Any idea about double buffering
  58. Representing the buffer with logic gates,flipflops
  59. vhdl
  60. VHDL Programming? Parallel Counter?
  61. fpga IOB
  62. fpga clock resolution
  63. VHDL configuration
  64. vhdl testbench help
  65. how to convert real to std_logic
  66. need help with VHDL code ....ARRAY
  67. Hi Needed Urgently
  68. SPR
  69. Wait on statement
  70. VHDL documentation tool
  71. Idea to implement ring buffer
  72. SCLive 3.0 With Verilog, VHDL, SystemC kernels available.
  73. procedure as argument in procedure
  74. How to Input a matrix in VHDL
  75. simulating records
  76. Situations in which 'else' or 'elsif' are unnecessary.
  77. Synthesis wrapper
  78. write(L, bitout(0)); -> cool but where yer two arguments?
  79. transaction recording
  80. TEXTIO drives me crazy!
  81. Philosophical placement of counter
  82. How can we get rid of all the spam in this group?? Aren't there somekind of filters??
  83. Dynamic Power Consumption Estimates/Comparison
  84. a quick query!
  85. Re: mapping input/output port
  86. how to define frame structure?
  87. Announcing Nov'11 FPGACamp, Silicon Valley. "Debugging Your FPGA"
  88. hey ppl????
  89. How to make custom types visible in other .vhd modules
  90. "Library unit is not available in library work"
  91. sig : process vs. process(sig)
  92. RS232 help!
  93. #Error loading design
  94. GNU Lesser Public License and Soft IP
  95. Modelsim under 64-bit Linux
  96. simulink modelsim cosimulation
  97. hi frnds
  98. Any body can explain whats wrong with this simple code ERROR:Xst:827
  99. c(0) <= a(0) + a(1); Found 0 definitions for operator "+"
  100. Source code encryption
  101. Synplicity tool
  102. External names vhdl2008
  103. [EN]&[IT] VHDL, memory hierarchy
  104. using multiple ranges
  105. Why use DSP builder over HDL?
  106. count until read next signal
  107. 2's compliment+parity+parallel to serial help please...
  108. VHDL for PCB design?
  109. Please recommand a VHDL book for synthesis purpose
  110. coregen help
  111. Signals too slow
  112. How to implement a counter
  113. Re: Spam on comp.lang.vhdl
  114. Image Processing in VHDL
  115. multiplier
  116. Checksum comparisons
  117. vhdl: wrong index type
  118. Re: Spam on comp.lang.vhdl
  119. Instantiating VHDL/Verilog modules (Generating the top level) usingan XML configuration file
  120. clock divider quetion
  121. Stopping the simulation in Modelsim Altera Starter Edition/Linux?
  122. how to implement this c++ algorithm in vhdl
  123. Verification Question
  124. Generic Multiplexer
  125. Testbench for geting currect time in ModelSim
  126. linking readable port names with indexed array
  127. Nike Shox Sneakers
  128. ∴∨∵∧∵wholesalw cap with factory price
  129. state machine help
  130. Writing a binary output file
  131. Newbie VHDL Blocks
  132. xilinx warning message
  133. clocked for loop with conditional if...
  134. ieee.math_real-support in Synplify for Lattice
  135. Re: How many bits?
  136. How many bits?
  137. Pointer clarification needed
  138. how 2 write vhdl for stepper motor
  139. How To Write Vhdl For Stepper Motor
  140. Mac OS X support for Sigasi HDT
  141. OT: Verizon will drop ALL newsgroups on 30 September
  142. ModelSim vs Aldec -- odd difference
  143. I'm looking for a review of Doulos VHDL courses
  144. Suggestion for Frame Handler Design
  145. Does ModelSim or any simulator software have a function similar tothe standard function any logic analizer has?
  146. std_logic_vector to string in hex format
  147. SPI, I2C and CPLD
  148. Assigning entire row in a 2d array?
  149. Help in VHDL for Test becnh signal generation
  150. Bus Emulation in Testbenches
  151. Post-Synthesis simulation runs into iteration limit
  152. record of a record to std_logic_vector
  153. Accumulator type DCO
  154. Why there is multi-source error?
  155. CFP - Journal of Systems Architecture, Embedded Software Design(Elsevier), Special Issue on Hardware/Software Co-Design
  156. how to pass input values to procedure
  157. Template for programming devices
  158. coding style for arithmetic operations
  159. Resource/operator sharing, good or not?
  160. Entity Generics Question
  161. Multi-source
  162. Real Random Number Generator
  163. Encoder counter problem
  164. vhdl code for Manchester
  165. conversion code
  166. a small clarification please
  167. Manchester representation
  168. serial stream data to capture in parallel line
  169. IP Core Wizard-Demystified
  170. using FIFO in vhdl
  171. how 2 write vhdl for dsp applications
  172. Loops for write access
  173. VHDL Testbench representation
  174. Using carry chain of counters for term count detect
  175. Re: Mixed language simulation on the cheap
  176. what is difference between generate and for loop in vhdl
  177. new version TimingAnalyzer
  178. Re: Mixed language simulation on the cheap
  179. Re: Mixed language simulation on the cheap
  180. Re: Mixed language simulation on the cheap
  181. Re: Mixed language simulation on the cheap
  182. Nonlinear Time Scale ModelSim
  183. Array assignment
  184. A few VHDL questions
  185. FPGA-Camp - A mini conference on FPGAs, (Aug'26, Silicon Valley)
  186. The HDL Complexity Tool beta testing.
  187. Reading a Vector to Create 5/9 Smoother
  188. VHDL record synthesis
  189. gtkwave-3.2.2 released
  190. Re: 3state/gate-based MUXes
  191. Re: 3state/gate-based MUXes
  192. Help with frequency divider
  193. Connecting an inout port to another inout port
  194. Reading 16 bit words from a file
  195. Why cant protected types be elements in an array?
  196. Synplify - Init Rom from file - Howto?
  197. HELP! Searching for research participants
  198. AM 2901 VHDL microprocessor slice
  199. Syntheis report??
  200. EVERAGE
  201. Xilinx BRAM initialization with .coe file
  202. VHDL code in Latex
  203. read from a file
  204. 8bit register with ALU computation
  205. How to make Unconstrained std_logic_vector port :)
  206. Stumped in Simulation Land
  207. VHDL process and function problem
  208. signal assignment and Delta delay
  209. Altera VS Xilinx
  210. Difference between two process
  211. Multiplication of 1 bit with vector
  212. CPLD Algorithm
  213. Fir Question
  214. Is there a way to extract vhdl code from an fpga?
  215. Synthesis VS Simulation
  216. Provider of EDA tool licensing and MPW services in Singapore
  217. Provider of EDA tool licensing and MPW services in Singapore
  218. xilinx bram not connected?
  219. Do you prefer paper or plastic... er, I mean paper or e-books?
  220. Using OPEN in port map
  221. Some support for VHDL project
  222. HELP required floating point multiplier on FPGA
  223. Can I include include a constant in a constant array?
  224. Re: Random distribution in VHDL
  225. Array of bits on to a signal in VHDL
  226. testbench question
  227. latch problem
  228. Why self defined type signal cannot assign value multiple times?
  229. Constants?
  230. Back to the future
  231. std_logic_textio library
  232. Interpolation in VHDL
  233. syncronizer
  234. Breaking parallel multiplier into two pieces in VHDL?
  235. Dual_port_BRAM
  236. How can I access a 2d array completely.
  237. issue with Chipscope
  238. How to force an internal wire which is deep inside DUT hierachy attop level testbench using VHDL design?
  239. modelsim doesn't like my increment w/wraparound
  240. Simulating Inverted Registers
  241. BAUD rate problem
  242. NEXYS2 Board from Digilent
  243. Adding signals of different size
  244. I've got a case of the latches....
  245. Need help initializing LPM_Add_Sub to do Sub
  246. FPGA / CPLD Group on LinkedIn -- Networking Group
  247. Expand unsigned 4*4 module to signed 16*16 module
  248. Re: pre-initialized dpram functional simulation
  249. Delay counters in three process state machines
  250. enum as array index