PDA

View Full Version : VHDL


Pages : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 [30] 31 32 33

  1. question of style
  2. question about spreading
  3. VHDL font
  4. Actel v. Xilinx
  5. WENG FOOK LEE- VHDL Coding and Logic Synthesis with Synopsys
  6. Newbie question about first project.
  7. VHDL verilog mixed design, strange problem
  8. pll frequency multiplier
  9. about use ieee.numeric_std.all
  10. [Q] how to use DesignWare function in Altra?
  11. interfacing Chameleon POD
  12. ANNOUNCE: MyHDL 0.4
  13. 16 QAM
  14. Variables
  15. Modelsim compile problem
  16. How to add an binary value to a vector?
  17. viterbi decoder design
  18. can we implement LIFO using SRL16 ???
  19. how to represent the negative value in data sequence?
  20. Mentor editor instead of ISE
  21. adaptive viterbi decoder design
  22. counter + somesteps
  23. counter question
  24. problem of real type in synthesis,
  25. Defining a real valued input in the entity
  26. QUES: ODFX/IDFX inferred in syplify, and not in XACT libraries ????
  27. alu implementation
  28. 4 bit divisor with flip-flop ?
  29. xlms in vhdl
  30. vhdl source code for DMA controller
  31. decoder
  32. newbie question about logging internal quantities
  33. fixed point multiplier in VHDL
  34. clock multiplier
  35. VHDL code for a microprocessor
  36. Simulation error
  37. Best way to mux addresses
  38. asynchronous counter an Xilinx FPGA for a newbie
  39. generic vector
  40. Still newbie question : Dialog between states machines.
  41. Connecting std_ulogic_vector to std_logic_vector
  42. VHDL code of PLL and LVDS-receiver for FLEX10K Altera PLD
  43. Connecting std_logic to std_logic_vector in component declaration
  44. Re: Best testbench style for microprocessor bus simulation
  45. EDK Modelsim Behavioral Simulation Error
  46. Network Traffic Models Generation
  47. FPGA / HDL full time job wanted
  48. Best testbench style for microprocessor bus simulation
  49. tutorial on vhdl simulation
  50. using the report statement inside package
  51. LFSR
  52. init RAM with .rif
  53. image sensors?
  54. FIR Filter
  55. PSL: New 2nd Edition book: Using PSL for formal and dynamic verification
  56. How to include don't care minterms
  57. newbie: vector increment????
  58. compiler of language C to openrisc processor with VHDL
  59. time set up
  60. Time set up
  61. CFP: 2004 MAPLD International Conference
  62. Loop exit
  63. newbye and Sonata / open_file problem
  64. Why do we hate variables?
  65. Synthesis errors?
  66. Portability
  67. How can I have multiple drivers of one inout port?
  68. Non static border in Loop
  69. product of real and (integer)(after converted to real one) value - vhdl found fatal error
  70. Tutorial on writing testbench files
  71. Newbie: what's the difference btn ':=' and '<='
  72. Packages, Components ??? How to organize a design ???
  73. QUES: Where can I find Xilinx M1 tools
  74. integer BCD converter in VHDL
  75. MicroBlaze User Peripheral with 2 interrupts
  76. PLUS3 in VHDL
  77. Memory Initialization Files in Modelsim
  78. newbie question on VHDL
  79. what does the sim.
  80. Bit-Level C Simulator
  81. FOO
  82. metastability
  83. Input Delay and Hold Time
  84. Design Compiler "ACS" feature?
  85. Convolution in VHDL
  86. Synplicity Synthesis of VHDL module
  87. Testbench HowTo Apply Hex Values from a File
  88. What does nios-run do?
  89. VGA
  90. Mod (%) Function in VHDL
  91. help with if ...(probably very lame question)
  92. SPARK C-to-VHDL Synthesis tool now supports Windows & Xilinx XST
  93. Integer or STD_LOGIC_VECTOR
  94. explanation
  95. "non-blocking" read in VHDL?
  96. How to generate a CSA tree?
  97. Error message in Mapping while using Xilinx ISE 6.1.03i
  98. image file reading in vhdl
  99. image file reading in vhdl
  100. Cypress Warp2 ROM Module File Format
  101. How put a signal value into REPORT ?
  102. Newbie Question: No Vsim, Vlib etc in my ModelSim
  103. More synchronization problems
  104. USB Code
  105. New HDLmaker release available
  106. SystemC
  107. USB CRC5 / CRC16
  108. Quantization levels of received symbol for viterbi decoder
  109. Openmore checklist
  110. My Sony Clie
  111. State Machine Output
  112. Counter help
  113. with ... select syntax
  114. subtype for integers
  115. chirpz transform in VHDL
  116. How do you initialize signals in VHDL?
  117. negative indexes
  118. Adding internal signals in Modelsim
  119. Specifying generics in configuration
  120. Is this correct?
  121. question for to_stdlogicvector( )
  122. Problem with loop
  123. please help! state machine
  124. AD: JTB FlexReport (FLEXlm license reporting tool)
  125. Newbie Question: Compiling VHDL in Mentor Graphics
  126. Flip Flop Synchronization
  127. problem with a state machine
  128. nclaunch ?
  129. Different concatenation result VJDL93' generates from VHDL'87
  130. Getting up-to-date libraries for timing simulation
  131. Dividing a clock
  132. Re: boolean to std_logic
  133. boolean to std_logic
  134. Mixing comb and reg part in one process
  135. SOS : 4-bit binary divider circuit PLEASE!!!!!!!
  136. FFT using Xilinx ISE
  137. parallel scrambler implementation
  138. Out of phase
  139. A difference between VHDL sources working
  140. error occured
  141. Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
  142. FLOATING POINT DIVISION
  143. FSM Problem
  144. Source to IEEE libraries
  145. Newbie - VHDL Storage
  146. information required
  147. Error: Actual is not a globally static expression
  148. Perhaps a newbie question...
  149. Clock and data extraction
  150. How Synopsys could save $$ without offshoring
  151. VHDL global signals
  152. HDLC
  153. Modelsim error code 211 : segmentation violation....What to do ???
  154. synthesisable floating point
  155. Why sensetivity list?
  156. predictable timing for xilinx cpld?
  157. How do we make an IP core????
  158. IEEE SOC Conference Call for Papers (Deadline April 16 2004))
  159. micron vhdl models gone ??
  160. Active-hdl
  161. search for netnames in design analyzer
  162. Verilog / VHDL
  163. VHDL comments in Vim?
  164. Signals across two clock domains
  165. generics in TB
  166. Internship in USA
  167. PSL tutotorial at designcon and dvcon
  168. Port types
  169. output
  170. Unknown signal resolution in NCsim and Modelsim
  171. Initialising a signal
  172. Hardware isssue
  173. Modelsim/Matlab co-simulation
  174. redundant signals in sensitivity list?
  175. non-static others choice
  176. hex notation
  177. hex notation
  178. Problem with Cadence's SimVision
  179. sens?
  180. Declaring ports with a complicated array type
  181. :(
  182. Coding error
  183. n_bit_demux
  184. ifft coding in vhdl give idea
  185. memory
  186. special FIFO
  187. VHDL information on internet
  188. Xilinx RAM16X1D for a Stratix?
  189. CODING PROBLEMS
  190. Modelsim error 211
  191. 8259A simulation using vhdl
  192. Have you adapted any software methodologies into your hardware work?
  193. How do I model a 6T SRAM cell in VHDL
  194. please help! unknown sintax errors with my code?
  195. December Offer ... Tyd-IP Code Generator Half Price
  196. CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD)
  197. N_bit decoder/encoder
  198. choice in a case satement
  199. Browsable VHDL syntax
  200. Synopsys & VHDL: **FFGEN**
  201. Map n algorithms to m functional units
  202. Integer Array - Help
  203. Implementation of parallel 2D median filtering
  204. Register problem(long)
  205. Using carry-in adders with Synopsys
  206. FAT32 Filesystem
  207. comp.lang.vhdl FAQ part 4 of 4: glossary
  208. comp.lang.vhdl FAQ part 1 of 4: general
  209. comp.lang.vhdl FAQ part 2 of 4: books
  210. comp.lang.vhdl FAQ part 3 of 4: products & services
  211. Ways to get the FAQ of comp.lang.vhdl
  212. Polar to Rectangular conversion
  213. [VirtexII + VHDL] problems with clock signals...
  214. "simple" problem
  215. component configuration, default binding, ModelSim
  216. Looking for a VHDL or Verilog RAM Model that modles Common RAM Faults
  217. How to design a 16 bit CISC processor ?
  218. Synthesis support for multi-dimentional arrays
  219. array of signed with unconstrained bit width (suggestions?)
  220. specific memory
  221. Help in choosing university for MS-PhD in VLSI
  222. Type Conversion in Procedure Call
  223. 'driving_value attribute
  224. file array read for ROM
  225. ANN: Tyd-IP Code Generator ....VHDL for DSP
  226. programmable FIR and simulation
  227. Buffer Mode Ports
  228. Libraries, packages and synthesis problems!
  229. modelsim error with synthesizeable VHDL
  230. vhdl coding of capacitor
  231. FIR coefficients
  232. A VHDL wannabe question
  233. Can a function be synchronous?
  234. FC II & Generic
  235. recursive description with generate and processes
  236. can anybody give me idea how to write vhdl coding for the IFFT of 8 point
  237. ERROR:Pack:1107 - ISE 6.1
  238. "Real" Simulations?
  239. verification vs validation
  240. Trouble with text output
  241. What is the state of state machine after power-up without reset conditions
  242. Signal assignment in state machine losing values
  243. floating point library
  244. avoiding GCLK
  245. how to write VHDL for shifting?
  246. VHDL Error
  247. Anyone use HDL as design tool for PCBs?
  248. Creating Library and Config Specification
  249. sensitivity list
  250. BCD counter and 7 segment LCD help.