VHDL [Archive] - Page 3 - Velocity Reviews

VSim et cygwin
difference between inertial and transport delay
Synthesis of Concurrent Statements for FIR Filter
Assigning arrays of different types
VHDL implementation of SPI for MAX6675
Re: Reed Solomon Encoder
can I specify a time-varying clock?
Testbench waveform problem, please help..
Why do shared variables HAVE to be a protected type?
Multiplication in VHDL
Re: How do variables get synthesized in this case?
Re: Variable Input on procedure - pass by value or pass by reference?
Re: Variable Input on procedure - pass by value or pass by reference?
Variable Input on procedure - pass by value or pass by reference?
Array of strings?
Looking for a VHDL simple description for RS-232
critical path
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Is this state machine written correctly?
Ddr Sdram
How to add delay in an output signal (without using clock) in cyclone 3 device?
How do variables get synthesized in this case?
clock divide by 5
Pseudorandom Noise Generator....
FFT using VHDL
JSA - Special Issue on Hardware/Software Co-Design
Viterbi Decoder Implementation
Successive arithmetic operations within a process
(refine question) vhdl and verilog simualtion
State machine incrementing
What's a slice in a FPGA ?
CFP with extended deadline of Mar. 17, 2009: The 2009 InternationalConference on Modeling, Simulation and Visualization Methods (MSV'09), USA,July 13-16, 2009
variable cnt1 : std_logic_vector(20 downto 0):= (cnt1'right => '1', others => '0');
"Independent" Simulation of Xilinx Project
Use verilog component in vhdl bench
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why is this code wrong? generic or others?
Error --unconstrained record or array type is not supported
Please help with Post-PAR simulation
combinatorial feedback loop
how to break out of for loop
high impedance in VHDL
Look for documentation
how can i extract a part of an image using VHDL !!
How to read 10 values at a time from a text file out of 50 values in VHDL
Timing Problems with counter
Integer arithmetic in HDLs
I can use std_logic_vector only as input signal in Xilinx?
How could I output a real signal to std_logic_vector?
Re: help with FSM
Modelsim command line: How to pass a generic parameter for my testbench ?
ERROR: Selector is an unconstrained array
Draft paper submission deadline extended: HPCNCS-09
Uart
Data Register Block
URGENT: How to execute an external program in vhdl?
Writing Test Bench
defparam
problem with synthesizing for loop
LINE to STD_LOGIC_VECTOR()?? and to_ASCII??
writing current date to a 32 bit register
Simple projects using VHDL
Pipelined signed multipliers
select configuration as a top-level for synthesize in Xlinx
File Transfer
CFP with extended deadline of March 11, 2009: WORLDCOMP'09 (The 2009World Congress in Computer Science, Computer Engineering, and AppliedComputing), USA, July 13-16, 2009
Should I be worried...
Unknown fault: signals not assigning
Search arithmetic library
ISE 10.1 and Timing Simulation Errors
use alias in port declaration?
Memory Controller for Cellular RAM + 128 word burst
for generate
BPSK demodulator
VHDL help.
Array issues
PID controller for DC motor
Verilog PWM DC motor
any way to avoid warnings about unused outputs in XST?
Test bench
ERROR: infix expression "<=" with simple vectors
Variable array size in entity
After Place and Route
VHDL - '+' operator Usage
transistor nMOS, pMOS
Last Call For Papers: WORLDCOMP'09 (Computer Science, Computer
Draft paper submission deadline extended: HPCNCS-09
Very fast counter in VirtexII
one hot state machine using for/generate
help me
need vhdl code
Compile time
Re: A "lurker thankyou" -was [Re: vhdl syntax query]
Help with creating a very small CPU
Random Value for LFSR (just simulation)
Illegal sequential statement error
one hot machine without elsif
Using a memory initialization file
Shift registers
Last Call for Papers: The 2009 International Conference on Modeling,Simulation and Visualization Methods (MSV'09), USA, July 13-16, 2009
Announce: new TimingAnalyzer version beta 0.92
vhdl code for reading an image
arrrrg!
Re: Multiple instances
Reading an Array of vectors.
unsigned(), unsigned'(), to_unsigned()
Re: division of two 4-bit vectors
Re: 4 digit input number
array of STD_LOGIC to STD_LOGIC_VECTOR
Re: division of two 4-bit vectors
Quartus II LPM simulation
Problem with clock
learning vhdl - state machines
ISE 10.1
Vhdl Projects Using Xilinx
Assignment to output signal from internal signal not istantaneous
using event attribute
Array initialisation - general questions
synchronous register
VHDL parser
Bit reversing
XC3S1000-4FT256
generic map problem
Problem with my counter
Re: Is this phase-accumulator trick well-known???
FIR ADDER IMPLEMENTATION
array problems
clk synchronization of reset signal
multiplier pipelining
Draft paper submission deadline extended: HPCNCS-09
clock generation by divide and reset
SPWM using vhdl
Testbench Question: Internal signals.
Hello, quick question
Xilinx Synthesis Problem
help in VHDL procedure programming
synthesis question of fixed point library
Which Verification Methodologies Are You Using?
reading binary files in vhdl. Use of read in a function.
Test vector for only MSB being set.
Implementation of Xilinx Aurora protocol with error correction
vhdl code
vhdl code
face recognition using neural networks
Automating VHDL Simulations in ModelSim
different between !=0 and >0 in the net list level
FIR Coefficients
generics depending on generics
Spartan 3A Starter Kit Comm Problem
Call For Papers: WORLDCOMP'09 (computer science, computerengineering, and applied computing conferences), July 13-16 2009, USA
verilog code errorneous
superposition of a square wave over a sine wave
superposition of a square wave over a sine wave
Test
"when others" question
Re: VHDL-2008 Now available from IEEE
Use of Implicit FSM Coding style
vhdl questions from a verilog person
VHPI Information
Need Help plz
conv_std_logic_vector function error - integer overflow
Why doesn't this work in an XC9572XL?
vhdl code
Conversion: double IEEE 754 => decimal ASCII-String
vhdl code
STD_LOGIC_VECTOR >> NATURAL ?
signed * unsigned is possible ?
Vlsi
concatenation - VHDL
Re: sw guy question about latches
problem in ISE with mealy FSM
Can not dowload the code into my Altera
Why can't I do simuation?
Re: sw guy question about latches
Re: sw guy question about latches
Process vs concurrent stataments?
Which VHDL Development Kit
Turning off Std checking in simulation
Problem with initialising a signed signal
Predefined attributes('Pos & 'Val) support issue in Synplify_pro
Initializing a signal externally
When did global signals become part of VHDL
SRAM "Hread" problem
SRAM Hread problem
Quad Port RAM
test pattern
Creating a core from my VHDL code
bit vector to real
hex constant
Change a constant value, depending on a generic
CFP: The 2009 International Conference on Modeling, Simulation andVisualization Methods (MSV'09), USA, July 13-16, 2009
reed soloman code
MOD operator
What functions ?
Unassigned register decode
Any one please write the state table...
aggregate assignments
[ANNOUNCE] MyHDL 0.6 released
signal sig_s2 can not be assigned, what is wrong with the code?
BIT, STD_LOGIC,STD_ULOGIC
please help for my State table
What does function unsigned'() do?
Re: Terminal Emulation for Console I/O
Terminal Emulation for Console I/O
OpenTech Package
std_logic_vector clock delay format
Decimal to binary conversion
HPCNCS-09 call for papers
Initializing a ram from file-- problem??
Re: Register with a default Value
How To Do Divsion Using Multi Dimensional Arrays...??
what is problem in this code....
Resolve function doesn't work
FPGA/CPLD Design Group on LinkedIn
VHDL NCSIM - map different library files
Verification automation using Tcl in ModelSim
Code Indentation
VHDL Races
multiple constant drivers for net IOP_
multiple constant drivers for net IOP_
Query on fractional divider logic
Call for Papers: WORLDCOMP'09: conferences in computer science,computer engineering, and applied computing, USA, July 13-16, 2009
Re: Selecting an Architecture to Instantiate
using GHDL and have problems with VCD dump option
LEON2-XST PCI Interface
Re: Selecting an Architecture to Instantiate
gtkwave website has moved
Functions don't work in declarations section
Re: modulo seems not to work when using in index
Re: modulo seems not to work when using in index
Re: modulo seems not to work when using in index
Glitch analysis tools for VHDL
Why MyHDL?
"Low-level vs High-level Programming" and a lot more...
Why no one ,no reply for this query??please reply me
Maybe hazard?
Finding MSB in a std_logic_vector
New features in VHDL 200x
Data alignment
problem with ise 10 synthesis
Register with a default Value
Any one please help for my project work..
FIFO not discarding data
"TO_X01" function
Re: From vhdl to verilog
XST internal error
Palladium 1 looking for a home
test-bench
array slice notation
leap year checking with vhdl