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  1. cast from sc_ufixed to int in systemC
  2. What is wrong with the following code?
  3. asynchronous design
  4. TRANSEDA VERIFICATION NAVIGATOR 2003 (WIN/LINUX) - new !
  5. vhdl for data forwarding in a pipeline machine
  6. Flex model concept?
  7. Modelsim 5.7c behaviour
  8. How can I use a new package?
  9. EAGLE v4.11 Professional *Bilingual* - Cadsoft (Windows, Linux - new !
  10. vhdl 1997 - 2002
  11. ModelSim & tcl testbench
  12. Ok, so now what?
  13. Good websites for Formal Verification ?
  14. beginner - exisit some free schematics programmer for fpga ?
  15. Printing Integer....
  16. vhdl toolkit without micro$oft?
  17. Aldec Riviera v2003.06.1059 WinNT2kXP - new
  18. Synplify doesn't like it...
  19. Simple I2C slave model (IO expander)
  20. Using nested, unconstrained array types?
  21. MENTOR_GRAPHICS_LEONARDO_SPECTRUM_V2003B, MODELSIM_SE_PLUS_V5.7F,NATIONAL_INSTRUMENTS_DIGITAL_WAVEFORM_EDITOR_V1.0,CST_DESIGN_STUDIO_V2.3, SYNOPSYS_FPGA_COMPILER_II_V3.8,SYNOPSYS_STAR-HSPICE_V2003.09, XILINX_CHIPSCOPE_PRO_V6.2i,XILINX_SYSTEM_GENERATO
  22. how to test benching a bidircetional port?
  23. how to test benching a bidirectional port
  24. HDL Hierarchy Manager 1.2.1 Announcement
  25. Hard Disk Drive behavioral model
  26. what do you guys do if Synopsys DC says it runs out of memory?
  27. HELP PLEASE!! - Finite State Machine - Automaton - Microprogrammed System
  28. time quantity in vhdl
  29. Clock edge during unstable input
  30. std_logic_vector divide
  31. CADENCE ORCAD UNISON SUITE PRO V10.0 - new !
  32. [Q] : async event counter
  33. array slices
  34. Postal Lottery: Turn $6 into $60,000 in 90 days, GUARANTEED
  35. file i/o in testbench
  36. procedure
  37. What happened to comp.lang.vhdl on google?
  38. PCB VERIBEST 1998 - 2002
  39. filters in vhdl
  40. Are there any good beginner book for VHDL
  41. HDL books for sale
  42. Functions
  43. optoisolated line
  44. complex generate usage in multiplier
  45. custom types in process sensitivity list
  46. Bit Error Rate...Implementation..
  47. Vhdl Cli bugs ??
  48. Virtex2 & ISE4.2
  49. FF with CE doesn't synthesize correctly by XST?
  50. Low-cost ASIC tools
  51. Primetime
  52. post-map simulation error
  53. Silly question....
  54. What are UNISIM/XilinxCoreLib/SIMPRIM and for what they are?
  55. Can't get to_integer to work
  56. Resume: Design Verification Consultant (Specman)
  57. reading the stimuls from input file
  58. ISE6.1: Constant definition in package doesn't work
  59. R: pullup on inputs
  60. pullup on inputs
  61. Reading from FPGA Issue
  62. problem with ise webpack 6.1
  63. dummy projects in VHDL/Verilog
  64. NEWBIE: Command line synthesis with Webpack
  65. atan in a FPGA
  66. Am I right in my VHDL code? Synopsys DC runs for ever...
  67. MOD function synthesis
  68. delta delay..
  69. VHDL Simulator Options
  70. How to print a long unsigned ?
  71. Integers only as generics?
  72. buffer port
  73. modeltech(modelsim) for linux platform, license?
  74. Home-made SSI chips
  75. how to implement gated clock and gated partial circuit in VHDL?
  76. dimension of an integer
  77. Dumping real signals in VCD
  78. SRAM vs Cache
  79. Seeking Free ASIC Design Kit.
  80. FS: IKOS NSIM 64 Simulation Acceleration Hardware
  81. R: useless synthetized blocks
  82. Type Error ??!! Any help
  83. Using LUTs for array of coefficients
  84. avoid the warnig
  85. useless synthetized blocks
  86. I'm looking for Altera Quartus II 3.0 License file
  87. Boundary scan clocking
  88. 4527 (bcd rate multiplier) vhdl code
  89. VHDL congress on Asia
  90. Importing Structural VHDL into Cadence 4.4.6
  91. Event
  92. 'STD_LOGIC_VECTOR ' to 'unsigned' type casting
  93. Multi-Source
  94. Is "integer" a keyword of VHDL?
  95. SystemVerilog: "logic" or "ulogic?"
  96. Counter with carry out at embedded bit.
  97. Actel Desktop Schematic Viewer
  98. OT: trouble with xilinx tool
  99. Hold Time Check Using a Procedure
  100. State machine: how to stay in a state?
  101. Re: When do I always put a "else NULL" statement in my VHDL code?
  102. PCI core and Cyclone
  103. Tristate
  104. About Latches and Registers was (When do I always put a "else NULL"statement in my VHDL code?)
  105. How to run a zero-delay simulation in a design with a RAM?
  106. will Synopsys Design Compiler automatically collect common sub expression to do intelligent optimization?
  107. ANN: VHDL IP protection by Source Code Obfuscation
  108. can I do such a simplest counter in VHDL?
  109. Looking for Atmel Dataflash VHDL model
  110. Re: When do I always put a "else NULL" statement in my VHDL code?
  111. what's the difference between VHDL 93 CONCATENATION and VHDL 87 CONCATENATION?
  112. Synthesis Tool Device Support Comparisions?
  113. NEWBIE ASKING FOR HELP! can anybody take a look at my Synopsys DC report?
  114. DDC design
  115. compilation error with ModelSim
  116. VHDL switch model
  117. A bus in a symbol with Viewlogic
  118. Re: When do I always put a "else NULL" statement in my VHDL code?
  119. bata takes too long with sun
  120. Re: When do I always put a "else NULL" statement in my VHDL code?
  121. SOS! What can I do if Synopsys does not allow my statement?
  122. Question - aggregates..
  123. MODELSIM cannot display the values of a variable?
  124. Is there any good book on PCI interface design?
  125. will Synposys Design Compiler support division by two's power and integer rounding?
  126. shall I reuse a variable/signal or not?
  127. where to define a type?
  128. I cannot simulate
  129. Re: understanding an error
  130. where can I find good samples for efficient computation of matrix multiplication?
  131. How can I infer resource re-use in my VHDL code?
  132. Open Source Vhdl Simulators?
  133. Record, Enumeration & std_logic_vector
  134. conversions
  135. Webpack Vs. ISE
  136. Tool survey for syntax for formal => actual
  137. Integer to slv
  138. Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL license
  139. equivalent types in different packages
  140. R: again on state machine
  141. R: again on state machine
  142. FFI against VHDL for test-benches
  143. again on state machine
  144. what is wrong with my VHDL code? I am so dissappointed...
  145. string declaration
  146. AWGN in VHDL
  147. R: decoder
  148. decoder
  149. Manipulating with the T1, T0 and TX in a SAIF file.
  150. Synthesizing a design with RAM.
  151. Are all the signals read in the process should appear in the sensitivity list of the process?
  152. Design Flow: STA to Synthesis
  153. Timing Diagram to HDL Translation
  154. IP-Core CAn-controller
  155. any VHDL books on low resource(throughput, area, power trade-off) design?
  156. SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed...
  157. predefined function/library
  158. what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes
  159. ModelSim and the Xilinix web pack unisim libraries
  160. Question: inout signal assignment
  161. Cpu Generator rel.1.00 released
  162. is function conv_std_logic_vector() synthesizable?
  163. switching problem
  164. How to get a slice of INTEGER type out?
  165. Re: R: warning?
  166. array of component
  167. Re: VHDL Newbie CAN Core questions
  168. warning?
  169. (newbie) 2 read/write register
  170. newbie question about <= and :=? what's the difference?
  171. function read_eeprom(addr); possible?
  172. (newbie) processo or not process?
  173. newbie question about decoder
  174. Prioritising nets
  175. newbie question about type declaration
  176. Re: VHDL Newbie CAN Core questions
  177. Simple combinatorial logic consuming major resources?
  178. Re: VHDL Newbie CAN Core questions
  179. Coding style to prioritize certain inputs
  180. Re: Complex digital ICs visual simulation?
  181. another newbie question about vhdl
  182. Complex digital ICs visual simulation?
  183. Anybody have MegaDecrypt 2
  184. Different types of ASICs?
  185. What does + synthesize to?
  186. Interfacing PDIUSBP11A to a Microcontroller
  187. generate testbench for array signals
  188. Configuration of multiple architectures
  189. VHDL design and ModelSim
  190. A student's question
  191. Using "others" in if statement
  192. Re: Hi
  193. where can I find book/resources talking about DSP design using VHDL?
  194. Re: Hi
  195. how to design this datapath unit for DSP using VHDL/Verilog?
  196. comp.lang.vhdl FAQ part 2 of 4: books
  197. comp.lang.vhdl FAQ part 3 of 4: products & services
  198. Ways to get the FAQ of comp.lang.vhdl
  199. comp.lang.vhdl FAQ part 1 of 4: general
  200. Inverted Clock in ACEX1K
  201. Re: Multiple event result
  202. (newbie) writing a state machine
  203. how to read and understand long written VHDL code?
  204. USB Controller
  205. create 400 clocks delay for a signal
  206. Re: VHDL question
  207. Address muxing from multiple sources
  208. assigning output to input
  209. others in state machine
  210. Re: Dynamic Configuration Possibility in Modelsim ?
  211. Hi
  212. Is it a bug of synplify?
  213. Please help me!!! ModelSim question
  214. Need help on how to use functions correctly
  215. simulation model of Motorola PowerQuicc 60x bus.
  216. Truth Table Implementation
  217. Re: Rant: VHDLisms
  218. How to connect pins of different width?
  219. Re: Signal within block
  220. Re: modelsim se error
  221. beginner
  222. Re: VHDL testbench: read BMP Files?
  223. Traversing Access types in Modelsim
  224. Re: VHDL testbench: read BMP Files?
  225. Re: VHDL testbench: read BMP Files?
  226. parameters for Routability estimation and analysis during RTL stages of the design.
  227. Re: VHDL testbench: read BMP Files?
  228. C++ Template Classes of Multi-Value Logic
  229. call for papers
  230. problem to convert integer to ascii chars for LCD in vhdl
  231. E language mode for Emacs
  232. Help with procedure
  233. Is transaction-based debugging useful ?
  234. ISE Foundation 4.1i compatibility
  235. Get value from a text file (newbie)
  236. graphics library vs Si engine
  237. Switch level simulation package
  238. bad synchronous
  239. Delay of control signals
  240. No Transmission Gate in Standard Cell Library
  241. Re: VHDLisms
  242. Re: VHDLisms
  243. Re: VHDLisms
  244. Re: VHDLisms
  245. Array (Newbie)
  246. Re: VHDLisms
  247. Which software from Xilinx
  248. Re: complement???
  249. help in cpu design
  250. VHDL for FPGA VME Slave