View Full Version : VHDL

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  1. issue converting of std_logic_vectors into integers
  2. VHDL ... What wrong with my real number???
  3. Components in VHDL
  4. Newbie Question
  5. spam
  6. spam
  7. interface (cdd to DE2)
  8. ASIC to FPGA porting/migrating
  9. simulation trouble
  10. problems using EMACS vhdl project
  11. Fractional Signed 2's complement representation
  12. Infix operator "+" Error
  13. Clock sampling with unisim FDCPE (virtex5)
  14. VHDL NAND flash model
  15. Re: Why does the placement of a statement mater in vhdl, I thought itwas a parallel language ?
  16. Re: Why does the placement of a statement mater in vhdl, I thoughtit was a parallel language ?
  17. error in quadrature design
  18. Re: Why does the placement of a statement mater in vhdl, I thought itwas a parallel language ?
  19. Declaring array of length 1
  20. Fifo
  21. Port sin LUT from VHDL to Verilog
  22. ISQED 2009 Call for Papers
  23. synopsys DC synthesis errors
  24. Data type used in VHDL
  25. Structured Verification Request for Information
  26. Avalda's Parallel F# to RTL FPGA Compiler
  27. Strange synthesis result , getting crazy
  28. Need Help, please take look my VHDL code.
  29. 8bit Limit on Enumerated Type?
  30. vhdl shifting command
  31. How can i do combination logic in VHDL
  32. how to solve implantation design with 4leds and 3DIP switches
  33. a small vhdl problem
  34. Truncate with fixed_pkg
  35. Can port Maps be expressions?
  36. State Machine with single cycle pulsed outputs?
  37. 2 Queries please
  38. reading strings with different lengths
  39. Generic Component Instantiation
  40. help~!
  41. pipeline
  42. deleting old transactions
  43. Basic question
  44. Basic question #2
  45. short announcement for TimingAnalyzer
  46. data types and arithmetic ops
  47. Basic question #3
  48. Basic question #4
  49. Speech recognition
  50. signals of record
  51. spam
  52. spam
  53. spam
  54. cpu 8051 dalton vhdl translated to verilog
  55. if and case cannot be considered equal
  56. Vector Waveform simulation test cases
  57. Problem with encoder
  58. pipe line in VHDL
  59. sane input
  60. Stopwatch
  61. question regarding passing generics in testbench
  62. regarding generics in a test bench.....with example .....
  63. Small problem in VHDL
  64. Xilinx cores with license
  65. SYNTHESIS QUESTIONS
  66. Variables are showing abnormal values in Time simulation
  67. POST PLACE and ROUTE SIMULATION
  68. SPI frequency range
  69. Best Synthesis Method
  70. Basic IEEE libraries question
  71. When Design Becomes Technology Specific ?
  72. Multi-source on Integers in Concurrent Assignment.
  73. Bidirectional Bus Modelling
  74. Event Driven State Machine
  75. stdio_h.vhd modules for string/file processing
  76. The Problem With most VHDL books
  77. receiving data
  78. State Variable latch error
  79. PG Diploma in VLSI Design using FPGA- new batch strating from 4th Dec08
  80. incompatible ouput files
  81. MULTIPLIER Inpots
  82. VHDL code for RS232 bus controller
  83. VHDL'93 instances sometimes mysteriously fail...
  84. spam
  85. spam
  86. spam
  87. Virtex-5 clocking
  88. Re: VHDL-2008
  89. VHDL state machine
  90. spam
  91. random and LEds question
  92. HELP!!!! array size confusion
  93. FIR test ?
  94. VHDL standard question (VHDL 93 chapter 4.3.2.2)
  95. Having problems with the following code???
  96. Need A Source Code For Bpsk Modulator
  97. synchronization of components
  98. Unexpected output in Post-translate Simulation
  99. Signal is not constrained
  100. Ambiguous type in infix expression
  101. how to read jpg file using VHDL
  102. std_match function
  103. Differences between different vendors implementations ofstd_logic_arith and the like
  104. Unique Opportunity To Join The Elite Group Of Project ManagementProfessionals
  105. Are constants not locally static?
  106. Use of std_logic '-' don't care.
  107. VHDL HELP!!!!! Kepad decoder code
  108. Re: VHDL-2008
  109. Coding State Machines
  110. Mapping entity and components
  111. I know Synopsys' Std_logic_arith/signed/unsigned is bad, but whatabout.....
  112. Byte lane select
  113. VHDL timing problem
  114. unsupported Clock statement. error message
  115. Multiplication
  116. Signal Processing Using VHDL
  117. How to write system verilog testbench assertions for a VHDL design
  118. Help....16 bit I/O on sprtan 3e
  119. ISQED09 Final Call for Papers
  120. spam
  121. Interesting EDK error !!!
  122. Comparator- something wrong
  123. how to program virtex 4?
  124. Altera Quartus II VHDL code compilation process
  125. example ucf file required
  126. vMAGIC 0.1.1 (alpha) released
  127. Connection to global signals
  128. ncshell for creating vhdl packages from verilo
  129. Timing Question
  130. TimingAnalyzer beta version 0.90 -- beta testers wanted
  131. Constants and signals in procedures
  132. ISE 9.2.03i problem
  133. compiling from 3 party editor
  134. vcd file generation in ncverilog tool
  135. Question about signals
  136. LRM question: What is the correct interpretation of an inout signalwith a default value that is left unconnected?
  137. Correct way of writing a mux followed by a register
  138. StateTable'LENGTH(2)
  139. about xilinx synthesizer.
  140. ARM AMBA Designer licensing cost
  141. RS-232 Receiver and Transmitter Design in VHDL
  142. PS/2 keyboard
  143. HPCNCS-09 call for papers
  144. needs help on CLOCK
  145. How IP cores are written
  146. DDC and NCO
  147. Route-Through
  148. Re: PN CODE GENERATOR
  149. the "|" operator
  150. process all elements of (unknown) records
  151. vhdl vector subtraction
  152. Adc
  153. Emacs VHDL-mode Compiler Setup
  154. niz microprocessor new version
  155. design of 2-bit adder in tree format
  156. Unsigned subtraction
  157. select file soorce/destination at simulation start
  158. Avoiding metastability on asynchronous inputs
  159. request: sample vcd files for TimingAnalyzer
  160. 7 segment display
  161. Design Question..
  162. Re: CREDIT CARD SERVISES
  163. synthesizing problem about complex numbers
  164. Compiling Error : "Value of index is not static"
  165. Moore State Change
  166. "Value of index is not static"
  167. to_stdlogicvector ERROR
  168. Design FIR filter in VHDL
  169. output TY = = -1.#INF ???
  170. floatfixlib synthesis
  171. How to define a constant of an array of records?
  172. Coding style to improve timing
  173. Signal Generator code
  174. Simple ALU Implementation
  175. Simple ALU Implementation
  176. Using Components in Processes
  177. using both rising edge and falling edge of signal
  178. How portable is this code?
  179. shift register
  180. near LIBRARY :Syntax error
  181. std_logic_vector'("0011100001111111") ??
  182. i am trying to use the sd ram of spartan 3 1800a dsp fpta
  183. Signal Conditional Assignment ?
  184. most significant and less significant address
  185. Complex testbench design strategy
  186. Need help with LAB assignment
  187. testbench
  188. Link for Joining the FPGA/CPLD Design Group on LinkedIn
  189. FOR LOOP in VHDL testbench?
  190. Re: Aligned PLL clocks in RTL simulation
  191. Re: Aligned PLL clocks in RTL simulation
  192. Re: Aligned PLL clocks in RTL simulation
  193. DOWNTO versus TO keyword on Component instantiation
  194. Re: Aligned PLL clocks in RTL simulation
  195. Halt synthesiser with an assert?
  196. Re: Aligned PLL clocks in RTL simulation
  197. vhdl code generators ( crossposted in comp.hardware.fpga)
  198. test bench