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  1. un-intentional gated clock after synthesis
  2. case expression and constants
  3. generic record exploration.
  4. Counter Question
  5. Modeling switches without bi-directional buffers
  6. ModelSim Error locally static expression
  7. Warning in Modelsim - vector truncated
  8. Count with specific bits of the counter
  9. n bit adder
  10. Help in VHDL!!!
  11. need help in using VHPI
  12. Relocating - need advice
  13. CRC Doubts
  14. Question about shifting
  15. What is "ASIC turnkey service"?
  16. VHDL question
  17. changes for synthesizable code
  18. [VHDL Beginner] About ressources used
  19. Design is too large for the device! xc3s400
  20. Synchronizer doubts
  21. Synchronizer doubts
  22. Using unregistered inputs in FSM
  23. Multiple input Adder
  24. timing simulation problem
  25. timing simulation problem
  26. help with incrementors
  27. VHDL vs. Verilog
  28. error trying to simulate NCO form quartus in matlab
  29. number of bits needed
  30. Query about tan inverse function
  31. Question regarding pragma translate_off/on , synthesis_off/on
  32. Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
  33. morre model
  34. Array of generic width std_logic_vector in entity?
  35. State Machine Approaches - A Revisit
  36. PACKAGE MATH_REAL problems
  37. Floating point synthesis
  38. MAPLD 2005: Program Announced and Registration Open
  39. instances of entities vs components
  40. Reading from STDIN for simulation
  41. Xilinx Conversion 3.1 --> 6.1
  42. Bazix introduce One Chip FPGA computer
  43. aggregate operator
  44. Detecting end of file for VHDL'93
  45. Help with advanced generic model
  46. VHDL-beginner question: output-value isn't stored
  47. verilog module instantantiation in VHDL top level
  48. reading synchronous RAM asynchronously?
  49. signal assigning question in FSM
  50. About AC97 audio controller
  51. Generic shift register where value 'n' keeps changing
  52. modelsim warnings
  53. Basic VHDL question regarding pins
  54. Compile model error
  55. configuration error
  56. Digital Down synthetizer
  57. Error Solving
  58. Active Conferences?
  59. help conversion code right one
  60. help conversion code
  61. fphdl package compilation error in Modelsim
  62. COMPILATION ERROR
  63. Intialization of State machine
  64. to access an array defined in some other file ?
  65. model sim errors in my design
  66. Q, logic value 'X'
  67. mandatory output binding?
  68. vhdl source cross-referencing tool
  69. model sim error in my design
  70. memory creation with record
  71. Sequential Circuits power up Reset
  72. Subtyping issue
  73. problem in my code
  74. Integer to std_logic_vector?
  75. TK simulation for 2-line LCD panel
  76. code error
  77. netlist from VHDL code
  78. netlist from VHDL code
  79. Hex files in simulation
  80. while loop
  81. comparing the array for generic parameters
  82. attribute signal name
  83. 'inout' procedure signal
  84. Specifying vector length in the function output
  85. comparing the array in parallel
  86. Modelsim breakpoint on end process.
  87. Synopsys clock edge question
  88. Or'ing output from conditionally generated instances
  89. array in vhdl
  90. How to save line in VHDL?
  91. Converting logic_vector -> natural
  92. Event counters for simulation only
  93. Uart and clock
  94. verilog to vhdl translation
  95. YOU ALL NEED TO SEE THIS JAW DROPPING PROOF THAT THE U.S. ADMINISTRATION WAS 100 % BEHIND THE SEPT 11 ATTACKS
  96. Log implementation in vhdl
  97. vhdl model length of wire with delay ?
  98. Problem in design
  99. Reading hex data from file
  100. ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL
  101. Array's of files
  102. [koma] [titlepage] Anschrift Links, Logo rechts
  103. What does this AHDL code mean?
  104. Need help with AHDL
  105. exiting from state machine
  106. comparing the contents of memory
  107. about addition operator
  108. DC vhdl question
  109. Help: what does this VHDL code mean?
  110. VHDL-plugin for jedit sidekick?
  111. Where is the bug?
  112. Bad synchronous description, but why ?
  113. Altera SCFIFO
  114. Post Translate Timing
  115. Books: Verilog and VHDL
  116. another array ranges mystery
  117. 1-element arrays are invalid in VHLD?
  118. modeling connecting Processor with memory
  119. modeling connecting Processor with memory
  120. Need standard function to do (Bool and Vector)
  121. N-Input Gate Using Loop or Generate
  122. Sensitivity list
  123. design boolean equations
  124. FIFO simulation
  125. binary to decimal
  126. component port mapping
  127. VHDL-AMS problem
  128. Turbo Decoder IP Core
  129. Out of range on type real?
  130. Help with syntesis warnings
  131. VHDL-200x fixed point package takes very long to synthesize
  132. single wire serial comms module
  133. hlp_needed in VHDL
  134. Increasing the Global Clock value inside the design ?
  135. VHDL boolean representation
  136. fast universal compression scheme and its implementation in VHDL
  137. I2C slave clock stretching
  138. AVR core and patents
  139. How to make a loop correctly?
  140. new to VHDL needs help
  141. an error on multi-source, but I can't understand...
  142. Q, howto setup 'unisim' for modelsim in linux
  143. edif2ngd warning
  144. VHDL -> PCB netlist ?
  145. Codec Video on FPGA
  146. VHDL Code Metrics
  147. Fast/low area Sorting hardware.
  148. AHDL graphic State Diagram and adding my own "type"
  149. wierd memory description
  150. Spartan 3 Starter Kit group formed
  151. 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
  152. why FSM so big
  153. extension_pack
  154. how to in INSTANTIATING large number of components?
  155. SRAM access times
  156. Help with state mahine resets
  157. help with serial to parallel conversion inside the fpga
  158. HOLD warning? Please comment on my code!
  159. Xilinx synthesis warning regarding clock nets
  160. real to integer conversion
  161. pass an undefined number of datasets
  162. parallel CRC equation generator
  163. process getting called more than once
  164. bit vs std_logic ?
  165. Help - Simulator CBS.
  166. ANN: Project VeriPage Update - New articles on SystemVerilog and PSL
  167. matched delays in Xilinx ISE?
  168. FATAL_ERROR:Xst:xstedge.c:128:1.4 ???
  169. 24 bit signed multiplier
  170. "else process" clause
  171. VHDL-200x-FT Place&Route problem in Quartus II
  172. ARM LINKS ANS DOCUMENTAION OF THE ARCHITECTURE
  173. Unconstrained array for output port in generic :/
  174. assert/report problems
  175. Bit stuffing in a Crc encoder
  176. Signed Adder without overflow
  177. 8bit counter to 7seg
  178. FSM with more than 1 input at each state
  179. Process Statements in VHDL
  180. dlx to three stages
  181. Hierarchies not the best for video pipelines
  182. while condition
  183. Good VHDL book for Verilog designer
  184. Simulation of rocket IO in virtex 2 pro
  185. Driving signals from a procedure
  186. Xilinx ISE : type real
  187. Warning:Xst:382 - Register A is equivalent to B
  188. Passing a signal from slow to fast clock
  189. Loop in procedure not complete
  190. NCSIM simulator
  191. wait for signal change
  192. vga controller
  193. Problem with Clock signals generated by combinational logic
  194. Why do VHDL gate level models simulate slower than verilog
  195. SDRAM AND MICROBLAZE PART 2
  196. clockdivider with enable
  197. State machine transition on internal signals -- is it legal?
  198. State machine transition on internal signals - is it legal?
  199. about hdl testbench
  200. Tristate-Master-Slave testbench description
  201. Advanced Synthesis Techniques
  202. VHDL-200x-ft packages
  203. Warning: Output pins are stuck at VCC or GND
  204. Looking for something others
  205. Synopsys vhdlsim (VHDL simulator)
  206. FSM simulation
  207. FSM in VHDL
  208. cannot be synthesized, bad synchronous description
  209. waiting on vector change
  210. MICROBLAZE AND SDRAM
  211. Gezocht: Ervaren VHDL programmeur
  212. HEX to STD_LOGIC_VECTOR
  213. Synopsys Design Analyzer in command prompt
  214. parameterizing number of ports?
  215. Variable 'variable lengths'
  216. What are these files?
  217. Linking problem in Primetime
  218. INFO:Xst:1304 -- precise definition anyone?
  219. pulse streatcher
  220. latches again
  221. extension pack
  222. Problem in array formation
  223. Text io in Xilinx
  224. Latches problem
  225. Case choice must be a locally static expression.
  226. i2c opencores
  227. can 2 if's to 1 if save 1 clock cycle?
  228. cf_fft
  229. about "super state machine"
  230. Generic, synthesizable synchronous 16x32 FIFO
  231. textio error
  232. An easy question for everyone
  233. Locally static?!
  234. Forum VHDL in Italiano
  235. Register Files for synthesis
  236. Case statement illusions ?
  237. post translate simulation
  238. Variable to signal assignment
  239. Re: Viterbi Decoder path memory using Block RAM
  240. Interfacing Digital Camera
  241. Interfacing Digital Camera
  242. Signal use from pin
  243. Flip Flop vs Registers
  244. Creating RAM in VHDL as Project
  245. Generic in CASE choice ?!?
  246. Synplify warning CL209
  247. How to instantiate identical components by for loop or generate in VHDL?
  248. dynamic size of ports
  249. PCI plug n play and Graphics card implementation
  250. Sync + FIFO