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- un-intentional gated clock after synthesis
- case expression and constants
- generic record exploration.
- Counter Question
- Modeling switches without bi-directional buffers
- ModelSim Error locally static expression
- Warning in Modelsim - vector truncated
- Count with specific bits of the counter
- n bit adder
- Help in VHDL!!!
- need help in using VHPI
- Relocating - need advice
- CRC Doubts
- Question about shifting
- What is "ASIC turnkey service"?
- VHDL question
- changes for synthesizable code
- [VHDL Beginner] About ressources used
- Design is too large for the device! xc3s400
- Synchronizer doubts
- Synchronizer doubts
- Using unregistered inputs in FSM
- Multiple input Adder
- timing simulation problem
- timing simulation problem
- help with incrementors
- VHDL vs. Verilog
- error trying to simulate NCO form quartus in matlab
- number of bits needed
- Query about tan inverse function
- Question regarding pragma translate_off/on , synthesis_off/on
- Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
- morre model
- Array of generic width std_logic_vector in entity?
- State Machine Approaches - A Revisit
- PACKAGE MATH_REAL problems
- Floating point synthesis
- MAPLD 2005: Program Announced and Registration Open
- instances of entities vs components
- Reading from STDIN for simulation
- Xilinx Conversion 3.1 --> 6.1
- Bazix introduce One Chip FPGA computer
- aggregate operator
- Detecting end of file for VHDL'93
- Help with advanced generic model
- VHDL-beginner question: output-value isn't stored
- verilog module instantantiation in VHDL top level
- reading synchronous RAM asynchronously?
- signal assigning question in FSM
- About AC97 audio controller
- Generic shift register where value 'n' keeps changing
- modelsim warnings
- Basic VHDL question regarding pins
- Compile model error
- configuration error
- Digital Down synthetizer
- Error Solving
- Active Conferences?
- help conversion code right one
- help conversion code
- fphdl package compilation error in Modelsim
- COMPILATION ERROR
- Intialization of State machine
- to access an array defined in some other file ?
- model sim errors in my design
- Q, logic value 'X'
- mandatory output binding?
- vhdl source cross-referencing tool
- model sim error in my design
- memory creation with record
- Sequential Circuits power up Reset
- Subtyping issue
- problem in my code
- Integer to std_logic_vector?
- TK simulation for 2-line LCD panel
- code error
- netlist from VHDL code
- netlist from VHDL code
- Hex files in simulation
- while loop
- comparing the array for generic parameters
- attribute signal name
- 'inout' procedure signal
- Specifying vector length in the function output
- comparing the array in parallel
- Modelsim breakpoint on end process.
- Synopsys clock edge question
- Or'ing output from conditionally generated instances
- array in vhdl
- How to save line in VHDL?
- Converting logic_vector -> natural
- Event counters for simulation only
- Uart and clock
- verilog to vhdl translation
- YOU ALL NEED TO SEE THIS JAW DROPPING PROOF THAT THE U.S. ADMINISTRATION WAS 100 % BEHIND THE SEPT 11 ATTACKS
- Log implementation in vhdl
- vhdl model length of wire with delay ?
- Problem in design
- Reading hex data from file
- ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL
- Array's of files
- [koma] [titlepage] Anschrift Links, Logo rechts
- What does this AHDL code mean?
- Need help with AHDL
- exiting from state machine
- comparing the contents of memory
- about addition operator
- DC vhdl question
- Help: what does this VHDL code mean?
- VHDL-plugin for jedit sidekick?
- Where is the bug?
- Bad synchronous description, but why ?
- Altera SCFIFO
- Post Translate Timing
- Books: Verilog and VHDL
- another array ranges mystery
- 1-element arrays are invalid in VHLD?
- modeling connecting Processor with memory
- modeling connecting Processor with memory
- Need standard function to do (Bool and Vector)
- N-Input Gate Using Loop or Generate
- Sensitivity list
- design boolean equations
- FIFO simulation
- binary to decimal
- component port mapping
- VHDL-AMS problem
- Turbo Decoder IP Core
- Out of range on type real?
- Help with syntesis warnings
- VHDL-200x fixed point package takes very long to synthesize
- single wire serial comms module
- hlp_needed in VHDL
- Increasing the Global Clock value inside the design ?
- VHDL boolean representation
- fast universal compression scheme and its implementation in VHDL
- I2C slave clock stretching
- AVR core and patents
- How to make a loop correctly?
- new to VHDL needs help
- an error on multi-source, but I can't understand...
- Q, howto setup 'unisim' for modelsim in linux
- edif2ngd warning
- VHDL -> PCB netlist ?
- Codec Video on FPGA
- VHDL Code Metrics
- Fast/low area Sorting hardware.
- AHDL graphic State Diagram and adding my own "type"
- wierd memory description
- Spartan 3 Starter Kit group formed
- 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
- why FSM so big
- extension_pack
- how to in INSTANTIATING large number of components?
- SRAM access times
- Help with state mahine resets
- help with serial to parallel conversion inside the fpga
- HOLD warning? Please comment on my code!
- Xilinx synthesis warning regarding clock nets
- real to integer conversion
- pass an undefined number of datasets
- parallel CRC equation generator
- process getting called more than once
- bit vs std_logic ?
- Help - Simulator CBS.
- ANN: Project VeriPage Update - New articles on SystemVerilog and PSL
- matched delays in Xilinx ISE?
- FATAL_ERROR:Xst:xstedge.c:128:1.4 ???
- 24 bit signed multiplier
- "else process" clause
- VHDL-200x-FT Place&Route problem in Quartus II
- ARM LINKS ANS DOCUMENTAION OF THE ARCHITECTURE
- Unconstrained array for output port in generic :/
- assert/report problems
- Bit stuffing in a Crc encoder
- Signed Adder without overflow
- 8bit counter to 7seg
- FSM with more than 1 input at each state
- Process Statements in VHDL
- dlx to three stages
- Hierarchies not the best for video pipelines
- while condition
- Good VHDL book for Verilog designer
- Simulation of rocket IO in virtex 2 pro
- Driving signals from a procedure
- Xilinx ISE : type real
- Warning:Xst:382 - Register A is equivalent to B
- Passing a signal from slow to fast clock
- Loop in procedure not complete
- NCSIM simulator
- wait for signal change
- vga controller
- Problem with Clock signals generated by combinational logic
- Why do VHDL gate level models simulate slower than verilog
- SDRAM AND MICROBLAZE PART 2
- clockdivider with enable
- State machine transition on internal signals -- is it legal?
- State machine transition on internal signals - is it legal?
- about hdl testbench
- Tristate-Master-Slave testbench description
- Advanced Synthesis Techniques
- VHDL-200x-ft packages
- Warning: Output pins are stuck at VCC or GND
- Looking for something others
- Synopsys vhdlsim (VHDL simulator)
- FSM simulation
- FSM in VHDL
- cannot be synthesized, bad synchronous description
- waiting on vector change
- MICROBLAZE AND SDRAM
- Gezocht: Ervaren VHDL programmeur
- HEX to STD_LOGIC_VECTOR
- Synopsys Design Analyzer in command prompt
- parameterizing number of ports?
- Variable 'variable lengths'
- What are these files?
- Linking problem in Primetime
- INFO:Xst:1304 -- precise definition anyone?
- pulse streatcher
- latches again
- extension pack
- Problem in array formation
- Text io in Xilinx
- Latches problem
- Case choice must be a locally static expression.
- i2c opencores
- can 2 if's to 1 if save 1 clock cycle?
- cf_fft
- about "super state machine"
- Generic, synthesizable synchronous 16x32 FIFO
- textio error
- An easy question for everyone
- Locally static?!
- Forum VHDL in Italiano
- Register Files for synthesis
- Case statement illusions ?
- post translate simulation
- Variable to signal assignment
- Re: Viterbi Decoder path memory using Block RAM
- Interfacing Digital Camera
- Interfacing Digital Camera
- Signal use from pin
- Flip Flop vs Registers
- Creating RAM in VHDL as Project
- Generic in CASE choice ?!?
- Synplify warning CL209
- How to instantiate identical components by for loop or generate in VHDL?
- dynamic size of ports
- PCI plug n play and Graphics card implementation
- Sync + FIFO
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