View Full Version : VHDL

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  1. entity parameterization
  2. What does 'SnKDone' signal stand for?
  3. VHDL expert puzzle
  4. Emacs, makefile and Aldec Riviera-Pro
  5. 8bits to 7segments bcd decoder
  6. signal AND with a constant of '1'
  7. 2 digit dice (random counter 1 - 6)
  8. Why on Simulation the result is not what is expected?
  9. Want to add signal timing waveforms in VHDL comments (any tools out there?)
  10. Time Divided by Time is What?
  11. Sting Signal into Vcd file
  12. defines both a type and a subtype
  13. Generating a 78MHz clock from a 100MHz base clock (VHDL)
  14. Generating a 78MHz clock from a 100MHz base clock
  15. Verilog Counter Question
  16. vhdl guessing game
  17. Can we log internal signals from a testbench in VHDL?
  18. search some good vhdl preprocessor (opensource)
  20. how to implement reed solomon encoder on fpga spartan 3e kit
  21. Hierarchical References out of generate block
  22. Is there a way to make testbenches assume simulation failure as default?
  23. What does this Verilog code do?
  24. verilog
  25. vhdl code for 8-bit galois field multiplication
  26. any simple way to load test vector in testbench that contains decimal format?
  27. Methods for flow control
  28. function printf in VHDL
  29. finite state machine- bad synch description
  30. doing sqrt( ) for synthesis.
  31. SLV reverse bit order
  32. Bidirectional bus connection
  33. Pipelining a large mathematical equation
  34. Concatenate/De-Concatenate
  35. Overflow on INTEGER value.
  36. Why a signal cannot control the file IO operation?
  37. internal signal delay problem
  38. FPGA - Offset in/out values
  39. operator vs. function
  40. fastest complex division algorithm
  41. VHDL programming
  42. Querying Active-HDL from TCL
  43. newbie with timing problem, is adding pipeline stages the only optionto speed up?
  44. how to start post synthesis simulation
  45. negative slack
  46. change variable in case statement
  47. change variable in case statement
  48. The International Conference on Computing, Networking and DigitalTechnologies (ICCNDT2012)
  49. Re: Why not mix concurrent and synchronous assignments in the same process?
  50. Problem with Comments in Emacs (want them to stop aligning)
  51. clk event at firs simulation cycle
  52. Re: Why not mix concurrent and synchronous assignments in the same process?
  53. vhdl-gui experience
  54. intialisation of matrix of integers
  55. inout pin problem
  56. "Open" banned on procedures - Is this an LRM thing?
  58. help for end of data
  59. Modelsim Problem
  60. Ko counter in Test Bench
  61. 1200 baud rate generator
  62. comparing characters from strings
  63. attribute signal name in procedure
  64. use vhdl program in matlab
  65. how can I drive an array from a component to the top level ??
  66. how to duplicate a component
  67. Re: VHDL Help
  68. State machine definitions
  69. Re: VHDL Help
  70. how to define a type with inputs and outputs like a bus
  71. Exporting a constant from component to it's parent
  72. signal and variable assignment problems
  73. alias: variable is an object but is not an object
  74. read binary file
  75. Probelm with modelsim.ini
  76. procedure call name vs.association_list ambiguity
  77. Unsupported clock statement error !!!
  78. Mixing different VHDL revisions between package and entity
  79. help with an error
  80. What about a new attribute to access the physical representation of a signal ?
  81. The definition of combinatorial process?
  82. Modelsim MXE on wine?
  83. A cheap or free version of VHDL?
  84. A cheap or free version of VHDL?
  85. What closes the implicitly open file?
  86. Call for beta users for Sigasi integration with Altera Quartus
  87. help needed regarding VHDL, GHDL and gtkwave
  88. wait for, vhdl
  89. Check all bits set
  90. Flipflops
  91. Counter defined as "integer range 0 to X"
  92. bcd-7segment decoder
  93. character to string
  94. File write of time & date
  95. Using numeric_std packages
  96. Help with instruction fetch unit in VHDL
  97. multiple individual bidirectional signal concatenated into 1bidirectional bus
  98. GHDL problems with (apparently) valid "alias"
  99. unsigned + std_logic
  100. divider algorithm
  101. Announcement: Sigasi integrates with Aldec compiler
  102. Types of bits
  103. Generic for port with array type
  104. sensitivity list in concurrent assertion
  105. vhdl IRC
  106. Tips for handling switch bounce?
  107. Coding timinig relationship
  108. Data conversion
  109. VHDL Type Mismatch error indexed name returns a value whose type does not match
  110. ERROR: Index name XXX is not static.
  111. Help with variables and 'for' loops
  112. case when <subtype> =>
  113. error in synthesis in vhdl code...
  114. dqpsk decoder
  115. signals VS variables
  116. Repeating Generate loop
  117. Re: Really Rusty in VHDL...
  118. Re: VHDL sound generator
  119. Shared variables and protected types
  120. bidirectional bus problem
  121. Re: Really Rusty in VHDL...
  122. Re: Really Rusty in VHDL...
  123. Is this a synthesizable code?
  124. Creating delay chain with generics
  125. VHDL ISA Bus Assignment Help
  126. Division
  127. VHDL automate help, beginner
  128. how to declare array???
  129. Behavior of VHDL comparison operator with integer argument
  130. State machine with D Flip Flop
  131. Ideas on higher level design
  132. Parametrized CLA adder in VHDL
  133. warning xst 2170
  134. Signed Arithmetic using VHDL Operators
  135. Problems switching to ieee.numeric_std.all
  136. waring in vhdl Xst:1355
  137. Counter with asynchronous enable
  138. Concatenate bits
  139. Concatenate bits
  140. modelsim error, help me
  141. video processing with FPGA
  142. VHDL code error
  143. building hierarcy error
  144. real to std_logic_vector conversion
  145. truncating std_logic_vector multiplication result question
  146. Audio Codec DE2-115
  147. vcs simulation problem
  148. VHDL program
  149. numeric_std package
  150. DE0-Nano g-forces
  151. Sync high freq to 100Hz?
  152. = to behave like std_match? (don't care)
  153. Detecting bit transistion in std_logic_vector
  154. crc-5
  155. the "Don't care" value
  156. summing of array elements in for loop
  157. Test process behaviour
  158. Why cant protected type methods have a parameter thats an access type?
  159. parallel CRC and ragged words
  160. Active-HDL/Xilinx Core FIFO Gen Sim Problem
  161. Stimulus Counter (from Opto-Sensors)
  162. problem in verilog coding
  163. Open file path specification
  164. Sanity check on a weird bit of math and std_logic_unsigned
  165. Spartan 6 MPMC - more ports?
  166. Open Source VHDL Verification Methodology
  167. Call For Papers: Journal of Engineering & Technology
  168. Re: GHDL and Tristate Busses
  169. Re: GHDL and Tristate Busses
  170. Is this a Ghdl/gtkwave bug?
  171. Is this a Ghdl/gtkwave bug?
  172. EPLD programming
  173. concurrent signal assignment: order can matter?
  174. can any one help me
  175. State machine - Vending machine - strange behaviour
  176. Testbench flow control with TCL
  177. A gray counter
  178. code synthesis problem
  179. convert boolean to std_logic
  180. Can a vhdl function return a range?
  181. psl assertion for dynamically created signal length
  182. Getting rid of packages in VHDL code
  183. Converted signed 16 Bit to unsigned?
  184. Convolutional Encoder VHDL
  185. How to make Clock Divider
  186. Error 10500
  187. Why isnt buffer used more often?
  188. Failure: (vsim-3807) Types do not match between component and entity for port "out1".
  189. Using Xilinx VHDL code with UNISIM on Altera toolset
  190. Cache Memory
  191. incremental generic association
  192. Will metastability not occur at the same clock domain?
  193. External name elaboration order
  194. Function result not locally static in case expression
  195. A python grepper script to split / select / filter VCD signals
  196. How do you use serial port or any other bus
  197. Pulse signal with variable working cycle controlled by a rotary control!
  198. quetion about verilog code..
  199. Case statements with double conditions? And an IF question.
  200. Modelsim - Simulation Fatal Error
  201. A Question About Concatenation in VHDL
  202. help with the testbench
  203. Counter with initial value
  204. dynamic power analysis for VHDL model
  205. golomb code
  206. Trilinear interpolation
  207. error using aggregates in port map
  208. SystemVerilog for verification
  209. VHDL code for water tank level
  210. help on choosing a strategy
  211. Using port map in a process
  212. Delaying Signals to Pipeline
  213. Gary's comment on languages
  214. Distributed Arithmetic in VHDL
  215. i have a doubt
  216. Direct entity instantiation...
  217. what wrong with my code? Traffice light controller State Machine
  218. PHDL a new HDL for PCB design
  219. Data flow, change with the time
  220. triangle wave generation
  221. 8bit Shift Add Multiplication Algorithm in VHDL: not synthesizing
  222. doubtfull code
  223. Problems with inout, please help!!
  224. Port map with if and process
  225. Floating-point Xilinx or Opencores?
  226. Test bench for a counter for vga hsync and vsync
  227. Alias array / array of aliases
  228. Type mismatch in testbench
  229. ror and sla in vhdl
  230. Problems with dynamic VHDL file IO
  231. Cambridge U.K and the use of verilog
  232. Embeding pipeline stages to a recursive adder tree code
  233. Generic N-bit multiplier
  234. <OT?> nonstandard use
  235. Image processing using VHDL
  236. Vhdl codes for edge detection
  237. Local packages
  238. Is there delta=0 except at the beginning moment?
  239. Would you like the alternative to Zero Ohm?
  240. Fast Counter
  241. Is this an LRM thing, or Modelsim Bug?
  242. Configuring FPGA bulk chips
  243. Re: Retrieving a signal parameter's name
  244. trouble connecting an out std_logic_vector port to aggregate of signals
  245. regarding thesis
  246. A free lunch
  247. VHDL and System Verilog Assertions
  248. Testbench\Package Signal Visibility
  249. PSL assertion book suggestion
  250. PSL book suggestions