View Full Version : VHDL

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  1. VHDL expert puzzle
  2. Emacs, makefile and Aldec Riviera-Pro
  3. 8bits to 7segments bcd decoder
  4. signal AND with a constant of '1'
  5. 2 digit dice (random counter 1 - 6)
  6. Why on Simulation the result is not what is expected?
  7. Want to add signal timing waveforms in VHDL comments (any tools out there?)
  8. Time Divided by Time is What?
  9. Sting Signal into Vcd file
  10. defines both a type and a subtype
  11. Generating a 78MHz clock from a 100MHz base clock (VHDL)
  12. Generating a 78MHz clock from a 100MHz base clock
  13. Verilog Counter Question
  14. vhdl guessing game
  15. Can we log internal signals from a testbench in VHDL?
  16. search some good vhdl preprocessor (opensource)
  18. how to implement reed solomon encoder on fpga spartan 3e kit
  19. Hierarchical References out of generate block
  20. Is there a way to make testbenches assume simulation failure as default?
  21. What does this Verilog code do?
  22. verilog
  23. vhdl code for 8-bit galois field multiplication
  24. any simple way to load test vector in testbench that contains decimal format?
  25. Methods for flow control
  26. function printf in VHDL
  27. finite state machine- bad synch description
  28. doing sqrt( ) for synthesis.
  29. SLV reverse bit order
  30. Bidirectional bus connection
  31. Pipelining a large mathematical equation
  32. Concatenate/De-Concatenate
  33. Overflow on INTEGER value.
  34. Why a signal cannot control the file IO operation?
  35. internal signal delay problem
  36. FPGA - Offset in/out values
  37. operator vs. function
  38. fastest complex division algorithm
  39. VHDL programming
  40. Querying Active-HDL from TCL
  41. newbie with timing problem, is adding pipeline stages the only optionto speed up?
  42. how to start post synthesis simulation
  43. negative slack
  44. change variable in case statement
  45. change variable in case statement
  46. The International Conference on Computing, Networking and DigitalTechnologies (ICCNDT2012)
  47. Re: Why not mix concurrent and synchronous assignments in the same process?
  48. Problem with Comments in Emacs (want them to stop aligning)
  49. clk event at firs simulation cycle
  50. Re: Why not mix concurrent and synchronous assignments in the same process?
  51. vhdl-gui experience
  52. intialisation of matrix of integers
  53. inout pin problem
  54. "Open" banned on procedures - Is this an LRM thing?
  56. help for end of data
  57. Modelsim Problem
  58. Ko counter in Test Bench
  59. 1200 baud rate generator
  60. comparing characters from strings
  61. attribute signal name in procedure
  62. use vhdl program in matlab
  63. how can I drive an array from a component to the top level ??
  64. how to duplicate a component
  65. Re: VHDL Help
  66. State machine definitions
  67. Re: VHDL Help
  68. how to define a type with inputs and outputs like a bus
  69. Exporting a constant from component to it's parent
  70. signal and variable assignment problems
  71. alias: variable is an object but is not an object
  72. read binary file
  73. Probelm with modelsim.ini
  74. procedure call name vs.association_list ambiguity
  75. Unsupported clock statement error !!!
  76. Mixing different VHDL revisions between package and entity
  77. help with an error
  78. What about a new attribute to access the physical representation of a signal ?
  79. The definition of combinatorial process?
  80. Modelsim MXE on wine?
  81. A cheap or free version of VHDL?
  82. A cheap or free version of VHDL?
  83. What closes the implicitly open file?
  84. Call for beta users for Sigasi integration with Altera Quartus
  85. help needed regarding VHDL, GHDL and gtkwave
  86. wait for, vhdl
  87. Check all bits set
  88. Flipflops
  89. Counter defined as "integer range 0 to X"
  90. bcd-7segment decoder
  91. character to string
  92. File write of time & date
  93. Using numeric_std packages
  94. Help with instruction fetch unit in VHDL
  95. multiple individual bidirectional signal concatenated into 1bidirectional bus
  96. GHDL problems with (apparently) valid "alias"
  97. unsigned + std_logic
  98. divider algorithm
  99. Announcement: Sigasi integrates with Aldec compiler
  100. Types of bits
  101. Generic for port with array type
  102. sensitivity list in concurrent assertion
  103. vhdl IRC
  104. Tips for handling switch bounce?
  105. Coding timinig relationship
  106. Data conversion
  107. VHDL Type Mismatch error indexed name returns a value whose type does not match
  108. ERROR: Index name XXX is not static.
  109. Help with variables and 'for' loops
  110. case when <subtype> =>
  111. error in synthesis in vhdl code...
  112. dqpsk decoder
  113. signals VS variables
  114. Repeating Generate loop
  115. Re: Really Rusty in VHDL...
  116. Re: VHDL sound generator
  117. Shared variables and protected types
  118. bidirectional bus problem
  119. Re: Really Rusty in VHDL...
  120. Re: Really Rusty in VHDL...
  121. Is this a synthesizable code?
  122. Creating delay chain with generics
  123. VHDL ISA Bus Assignment Help
  124. Division
  125. VHDL automate help, beginner
  126. how to declare array???
  127. Behavior of VHDL comparison operator with integer argument
  128. State machine with D Flip Flop
  129. Ideas on higher level design
  130. Parametrized CLA adder in VHDL
  131. warning xst 2170
  132. Signed Arithmetic using VHDL Operators
  133. Problems switching to ieee.numeric_std.all
  134. waring in vhdl Xst:1355
  135. Counter with asynchronous enable
  136. Concatenate bits
  137. Concatenate bits
  138. modelsim error, help me
  139. video processing with FPGA
  140. VHDL code error
  141. building hierarcy error
  142. real to std_logic_vector conversion
  143. truncating std_logic_vector multiplication result question
  144. Audio Codec DE2-115
  145. vcs simulation problem
  146. VHDL program
  147. numeric_std package
  148. DE0-Nano g-forces
  149. Sync high freq to 100Hz?
  150. = to behave like std_match? (don't care)
  151. Detecting bit transistion in std_logic_vector
  152. crc-5
  153. the "Don't care" value
  154. summing of array elements in for loop
  155. Test process behaviour
  156. Why cant protected type methods have a parameter thats an access type?
  157. parallel CRC and ragged words
  158. Active-HDL/Xilinx Core FIFO Gen Sim Problem
  159. Stimulus Counter (from Opto-Sensors)
  160. problem in verilog coding
  161. Open file path specification
  162. Sanity check on a weird bit of math and std_logic_unsigned
  163. Spartan 6 MPMC - more ports?
  164. Open Source VHDL Verification Methodology
  165. Call For Papers: Journal of Engineering & Technology
  166. Re: GHDL and Tristate Busses
  167. Re: GHDL and Tristate Busses
  168. Is this a Ghdl/gtkwave bug?
  169. Is this a Ghdl/gtkwave bug?
  170. EPLD programming
  171. concurrent signal assignment: order can matter?
  172. can any one help me
  173. State machine - Vending machine - strange behaviour
  174. Testbench flow control with TCL
  175. A gray counter
  176. code synthesis problem
  177. convert boolean to std_logic
  178. Can a vhdl function return a range?
  179. psl assertion for dynamically created signal length
  180. Getting rid of packages in VHDL code
  181. Converted signed 16 Bit to unsigned?
  182. Convolutional Encoder VHDL
  183. How to make Clock Divider
  184. Error 10500
  185. Why isnt buffer used more often?
  186. Failure: (vsim-3807) Types do not match between component and entity for port "out1".
  187. Using Xilinx VHDL code with UNISIM on Altera toolset
  188. Cache Memory
  189. incremental generic association
  190. Will metastability not occur at the same clock domain?
  191. External name elaboration order
  192. Function result not locally static in case expression
  193. A python grepper script to split / select / filter VCD signals
  194. How do you use serial port or any other bus
  195. Pulse signal with variable working cycle controlled by a rotary control!
  196. quetion about verilog code..
  197. Case statements with double conditions? And an IF question.
  198. Modelsim - Simulation Fatal Error
  199. A Question About Concatenation in VHDL
  200. help with the testbench
  201. Counter with initial value
  202. dynamic power analysis for VHDL model
  203. golomb code
  204. Trilinear interpolation
  205. error using aggregates in port map
  206. SystemVerilog for verification
  207. VHDL code for water tank level
  208. help on choosing a strategy
  209. Using port map in a process
  210. Delaying Signals to Pipeline
  211. Gary's comment on languages
  212. Distributed Arithmetic in VHDL
  213. i have a doubt
  214. Direct entity instantiation...
  215. what wrong with my code? Traffice light controller State Machine
  216. PHDL a new HDL for PCB design
  217. Data flow, change with the time
  218. triangle wave generation
  219. 8bit Shift Add Multiplication Algorithm in VHDL: not synthesizing
  220. doubtfull code
  221. Problems with inout, please help!!
  222. Port map with if and process
  223. Floating-point Xilinx or Opencores?
  224. Test bench for a counter for vga hsync and vsync
  225. Alias array / array of aliases
  226. Type mismatch in testbench
  227. ror and sla in vhdl
  228. Problems with dynamic VHDL file IO
  229. Cambridge U.K and the use of verilog
  230. Embeding pipeline stages to a recursive adder tree code
  231. Generic N-bit multiplier
  232. <OT?> nonstandard use
  233. Image processing using VHDL
  234. Vhdl codes for edge detection
  235. Local packages
  236. Is there delta=0 except at the beginning moment?
  237. Would you like the alternative to Zero Ohm?
  238. Fast Counter
  239. Is this an LRM thing, or Modelsim Bug?
  240. Configuring FPGA bulk chips
  241. Re: Retrieving a signal parameter's name
  242. trouble connecting an out std_logic_vector port to aggregate of signals
  243. regarding thesis
  244. A free lunch
  245. VHDL and System Verilog Assertions
  246. Testbench\Package Signal Visibility
  247. PSL assertion book suggestion
  248. PSL book suggestions
  249. help with binary decoder
  250. help with binary decoder