View Full Version : VHDL

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  1. How to use 'assert' and 'report'
  2. shift_right/ shift_left
  3. Some System Verilog questions
  4. nested if-elsif-then Vs case
  5. Decoder using VHDL
  6. Post Synthesis, Post PAR, and real hardware behavior?
  7. clock and stable data
  8. BCD Counter
  9. Modelsim simulation progress in batch/command line mode?
  10. driving "external" signals from a procedure
  11. how to download matlab program onto fpga
  12. Question on bounce filter
  13. dumpports:pullup and pull down (problem )
  14. Implementation of an up/down counter in a Xilinx Spartan 2E board
  15. Calling functions declared in an entity
  16. VHDL Case Statement
  17. analog to digital converter
  18. gray counter and compare value
  19. VHDL and Emacs (My experience)
  20. About textio
  21. debounce state diagram FSM
  22. how using files as input and outputs
  23. fast synthesize
  24. VHDL Instance statement
  25. fast ISE bitfile making!
  26. Xilinx Core Asynchronous FIFO Limits not being set
  27. configuration problem
  28. Error message using Modelsim in Linux
  29. Define type based on function return in package?
  30. Doese CoreGen RAM can be simulated in ModelSim?
  31. Board and VHDL
  32. Multiple copies of an entity controlled by a parameter 'b'
  33. code 211 in modelsim / Xilinx ISE sim problem
  34. Using signals in VHDL design
  35. Edge detector
  36. VHDL and reading of picture
  37. re-use of a mask(kernel) ...on Vhdl
  38. Simulation : Extracting dataflow to create a file
  39. Simulation : Access internal signals
  40. determine slv width by given integer range
  41. Prefix of indexed name must be an array.
  42. Could not find instance error
  43. size of std_logic_vector to unsigned
  44. Recurse wait not supported or bad place of Exit or Next statement (Error msg)
  45. Atom HDL
  46. vhdl compiling error message
  47. State encoding
  48. Compiler complains about non-synthesizable aggregate
  49. VHDl AMS questions
  50. Modelsim Tcl script Problem
  51. intel 8279 VHDL code wanted
  52. convert a variable of type TIME into a REAL?
  53. address decoder (once more)
  54. DMA ipif plb
  55. Actual for formal is not a signal
  56. VHDL question - how can I know a clock cycle is over?
  57. Parameterisable number of shift reg components
  58. Seven Segment for decimal numbers
  59. What is the difference between 'std_logic_vecotor' and 'signed'
  60. What is the difference between 'std_logic_vecotor' and 'signed'
  61. Daughter Cards, Headers, INOUT
  62. How to wait few nano seconds in a Process?
  63. Register will not change
  64. COMPONENT fjkce and warning
  65. onboard DDR testing !
  66. Searching a behavior model for an Ethernet Phy in VHDL
  67. Signals in VHDL
  68. gtkwave not displaying ghdl simulation.
  69. How do I use the memory lock facility in LInux
  70. compilation directive
  71. simulation problem
  72. dual-edge sensitivity
  73. Test vectors for emulator.
  74. code synthesis problem in file read operation
  75. ceiling VHDL function
  76. CMOS camera-FPGA-USB
  77. Timer ...
  78. function with given range attribute as argument
  79. two-dimensional array, assign to zero, vhdl
  80. cache not a ROM, inferring, xilinx
  81. Need to delay a signal a great number of clk cycles
  82. generate?
  83. 6x6 kernel from a 3x3
  84. Anyone using the TimingAnalyzer
  85. Urgent Question.
  86. ANNOUNCE: Zeus for Windows IDE Version 3.96f
  87. LF VHDL to FSM bubble diagram translator
  88. Interfacing DDR RAMs to Xilinx Virtex 2 Pro on Digilent boards
  89. Single clock pulse transfer to different clock domains.
  90. How do i make a race timerA in VHDL?
  91. Conflicting results
  92. Same code ... Different results ...
  93. VHDL newbie: building sequential circuits with basic gates
  94. Modelsim 6.3 & VHDL2006
  95. VHDL Test Bench Package Release
  96. SystemC and TLM
  97. Conditional "FOR..GENERATE" generic construct?
  98. How to insert tab in Write() function in VHDL
  99. How do I constraint multiple clock cycle in Altera?
  100. generate stimulus in a 'do' file
  101. 11bit or 12 bits ?
  102. Reed Solomon Encoder
  103. Book on vhdl and board
  104. UART Receiver Parity Check
  105. Initializing memory to random numbers
  106. component usage
  107. Call For Participation: WORLDCOMP'07: joint conferences in CS, CE, and applied computing, June 25-28, 2007, Las Vegas
  108. quwstion from newbie
  109. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
  110. Query about optimization
  111. What you suggest?
  112. Node instance
  113. How many memory need for Convolution
  114. Re: Query about optimization
  115. Re: Query about optimization
  116. Binary to BCD in VHDL
  117. Differfence in the assignment of a variable to a signal with and without condition
  118. Re: Node instance
  119. Re: Node instance
  120. Re: Node instance
  121. Re: Node instance
  122. Re: Node instance
  123. Re: Node instance
  124. Detecting TTL
  125. design flow questions
  126. Custom Software Development
  127. Multiple sources ??? Example vhdl code - anyone can help ???
  128. Multiple sources ??? Example vhdl code - anyone can help ???
  129. MODELSIM : library generation and mapping
  130. Simulation of VHDL in xilinx from a C program?
  131. Are actions permitted on rising *and* falling edge of clock?
  132. How can I flush file input buffers?
  133. How to Dart Game with VHDL
  134. visualise"type" in wave window
  135. floating number
  136. Question on FIFO
  137. warning: vcom-1186
  138. warning: vcom-1186
  139. Quartus II Warning: Found pins functioning as undefined clocks
  140. state machine and register infering
  141. VHDL syntax problem? Xilinx problem?
  142. Questions about single process coding style
  143. error in post route simulation plz help
  144. Counter
  145. polynomial divisor reminder
  146. Building Gradually Expertise on VHDL/Verilog Design
  147. two .vhd sources in a project... ISE 9.1 ?
  148. data compression algorithms on FPGA
  149. multiline comment?
  150. any body having complete code for a synchronous FIFO or know a link where FIFO codes are available
  151. any body having complete code for a synchronous FIFO or know a link where FIFO codes are available
  152. "Wait on" instead of "Sensitivity List" does not work???
  153. any body having complete code for a synchronous FIFO or know a link where FIFO codes are available
  154. any body having complete code for synchronous fifo or know a link where fifo codes are available plz help
  155. Great Computing Surface for Road Warriors
  156. help with a problem compiling
  157. vector align on fixed boundaries
  158. What to do when post-synthesis simulation do not pass
  159. integer range restriction
  160. trying to understand timings of 74LS74
  161. tasks in differenet rising edges.
  162. Questions about single process coding style
  163. generate and std_logic_vector array issue
  164. Changing a variable when simulating??
  165. read data file?
  166. Mesa 5i21 Xilinx
  167. PC => FPGA, Parallel Port Communication
  168. Portable TCP/IP socket library
  169. 32-Bit Fixed Point Divider Needed
  170. reading binary file
  171. DragonFly
  172. Connecting two bidirectional ports together
  173. Warning: Global clock buffer not inserted on net rtlc1n42
  174. General question on the simulation of VHDL-code with Alteras QuartusII
  175. Current module quartus_map ended unexpectedly
  176. Arbiter
  177. latch and flipflop
  178. generic check
  179. Adding a NATURAL and a STD_LOGIC_VECTOR
  180. Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
  181. ERROR MESSAGE IN MODELSIM
  182. one hot< two hot in FSM encoding
  183. how to use "wait" or dealy in a process?
  184. dcm error
  185. RC4 - someone help pleas!!
  186. Call For Participation: WORLDCOMP'07: joint conferences in CS, CE, and applied computing, June 25-28, 2007, Las Vegas
  187. Type conversion (to unsigned) can not have aggregate operand.
  188. Question on importing text from files
  189. Synthesis of variable index array
  190. Method cannot have a parameter of file type
  191. Method cannot have a parameter of file type
  192. round robin?
  193. 74163 for 2bit counter
  194. ANNOUNCE: Atom 2007.06
  195. GHDL and Xilinx
  196. Synchronize incoming singal to clock
  197. DCM clock signal output
  198. VHDL VGA controller
  199. LFSR
  200. funtions
  201. 3x3 sobel edge detection
  202. shift/rotate operator for std_logic_vector
  203. str to stdvec of converted values
  204. modelsim 6.3 license
  205. i can't simulate with modelsim XE III 6.2C
  206. EPP Data Write Cycle
  207. Accellera VHDL 2006 LRM
  208. low attribute
  209. What does "others : begin NO" mean?
  210. Generic RAM Implementation
  211. How Do Perform STD_LOGIC_VECTOR Addition Using IEEE.NUMERIC_STD?
  212. Case Statement understood as FSM
  213. Time of Synthesis
  214. CORDIC algorithm in vhdl
  215. New versions of fixed and floating point packages
  216. ANNC: LatticeXP2 FPGA Introduction Webcast
  217. VHDL to Verilog conversion
  218. What is the meaning of a signal in VHDL
  219. Cadence TestBuilder
  220. Cadence TestBuilder
  221. VHDL Eclipse Plugin
  222. Procedure call
  223. On HDL Synthesis
  224. My FSM is jumping to an unreachable state
  225. Tdm Bidirectional Serial Line
  226. Counter in FSM doesn't work
  227. cdma receiver
  228. Problem with ASSERT ... REPORT and NUL
  229. Delay in FSM using one process
  230. access internal signal in VHDL from verilog
  231. 'for' loops in VHDL
  232. Re: 'for' loops in VHDL
  233. Re: 'for' loops in VHDL
  234. VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
  235. USB NRZI encoding and bit stuffing question
  236. counter with reset which is synchronous with one of two clocks
  237. "IF" condition & STD_LOGIC_VECTOR
  238. Vhdl C++
  239. Timing details during synthesis in Xilinx ISE
  240. a crazy problem
  241. Width issues in Synplify Pro 8.8
  242. More width issues in Synplify Pro 8.8
  243. Can I Pass a 2D Array as a Parameter to a Procedure?
  244. default value for subprogram parameter
  245. subtype question
  246. Does VHDL have a statement similar to "event" in Verilog?
  247. clock delay when testing different inputs in FSM ?
  248. memory implementation
  249. Integer in port declaration?
  250. VHPI Books and/or Tutorials