View Full Version : VHDL

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  1. Delta Delays
  2. Carry Save Adder (CSA) Verilog code
  3. Warning ==> Latches
  4. two-dimensional arrays cannot be simulated
  5. Xilinx-altera-problem
  6. FFT in VHDL (or Verilog) Tutorial
  7. help please
  8. MODULUS operator
  9. Is there a way to combine verilog and vhdl?
  10. using files for testbench
  11. Syntax help
  12. Problems with GHDL and GTKWave
  13. VHDL Help with Spartan 3
  14. 'event attribute & modelsim 6.0 problem
  15. Problems with Opencores' I2C "READ" function
  16. conv_integer simulation whining in ISE
  17. signed multiplication
  18. how to add a new library in xilinx.
  19. Changing files
  20. reading files help
  21. Modelsim Assert
  22. VHDL to Verilog Converter
  23. Circular dependency problem
  24. GOOD REFFERENCE BOOK NEEDED
  25. Bi-Directional Bus inside Spartan 3
  26. ISE Bug?
  27. Sign extension
  28. Having access to a VHDL "signal" using ModelSim
  29. Having access to a VHDL "signal" using ModelSim
  30. How to find the ABS of std_logic_vector
  31. opencores projects
  32. i need a help to solve a problem in VHDL
  33. Post Synthesis VHDL
  34. I2C "READ" Setup/Hold Requirement
  35. change initial value of state machine
  36. Data checking
  37. Data checking
  38. ADC and DAC Converters VHDL model
  39. Creating a delay with VHDL without using wait (n00b)
  40. Error: VHDL Use Clause error at quartustest.vhd(6): design library "IEEE" does not contain primary unit "std_logic_textio"
  41. MIG tool DDR1 interface !
  42. cosimulate VHDL with Simulink help need
  43. LOAD on asynchronous RESET
  44. XC2S30 with display VQC10
  45. What's Nonpipelined bus mean?
  46. Problem with Fix_std
  47. AMD/Spansion FLASH problem
  48. Modelsim: have the compile report in the transcript window ?
  49. simple state machine
  50. Verilog Ref Book
  51. Counter Glitches Question
  52. Timing constraints in an FPGA
  53. Modelsim AE / multiple waveform windows
  54. Saving results from a simulation
  55. Synchronizer theory and question
  56. Question about conditional generate
  57. Question about conditional generate
  58. problems with verilog SDRAM models
  59. where are wombats?
  60. are wombats good?
  61. junk/garbage posts
  62. inverse function, how?
  63. How to meet timing constraints in an FPGA
  64. Help with assert statement
  65. VHDL vs. System Generator, et al.
  66. How to describe this block diagram in VHDL?
  67. Comparing counters in two different clock domains
  68. Netlist simulation
  69. procedure overloading vs. ?
  70. How to calculate amplitude and phase of a digital/analog signal in VHDL?
  71. Matlab and VHDL
  72. FFT in AHDL
  73. Integer arithmetic
  74. Reconfigurable PLL
  75. Data structures and signals and stuff.
  76. problem in optimization of top level
  77. viterbi implementation on actel fpga
  78. multiplier
  79. The best way to implement this non-power-of-two modulo-like function on a limited subtype?
  80. Global Clock
  81. viterbi decoder
  82. Call For Papers/Sessions: WORLDCOMP'07: multiple int'l. conferences in computer science & computer engineering, USA
  83. numeric_std omissions
  84. how can I set outputs high on startup?
  85. Variable Input file length
  86. Divison Operation
  87. Graphics engine IP
  88. More Configuration Problems
  89. CMI Coder/Decoder
  90. Synchronizing two different clocks
  91. Partial Aggregate Assignment
  92. FFT on Virtex II Pro (how to download .dat file?)
  93. FFT on Virtex-II Pro (how to download .dat file?)
  94. Urgent Requirement for ASIC Verification Engineers in CA
  95. Urgent Requirement for ASIC Verification Engineers in CA
  96. computer vision projects for open cores
  97. problem in vhdl code with a one clock delay
  98. ModelSim SE 6.1f : code coverage database merge problem
  99. Book and a starter kit
  100. Simple question about if statemets
  101. Objects list at ModelSim
  102. conv_std_logic_vector
  103. VHDL 2 VERILOG CONVERTER FOR AHB
  104. Mapping signals to components
  105. Fpga
  106. DDR2 VHDL model
  107. Synopsys SMP3 Reference Model
  108. gate logic synthesis
  109. GUI Based vs. Manual Instantiation of Components
  110. Quartus II compilation too slow for RAM design
  111. regards NULL character reading
  112. regards NULL character reading
  113. lib & package
  114. multiplying std logic vectors
  115. Lcd Block Diagram - Vhdl - On Fpga.. help!
  116. Merging arrays in Modelsim
  117. Xilinx .npl to .ise can't convert
  118. hi friends, pls guide me to find ASIC Verification Engineers with VERA or Specman expereince
  119. OT : Bug/Issue tracking systems
  120. connection
  121. function and its hardware?
  122. unexplainable Problem on Spartan 3
  123. A question about variable thing
  124. parser VHDL to DOT (graphviz)
  125. Warning message
  126. Tracing UNKNOWN drivers
  127. Tracing UNKNOWN drivers
  128. last_value
  129. Embedded Development Tools
  130. Matlab (.m) to VHDL
  131. A Sorting Circuit in Digital Logic Design
  132. Does VHDL accept floating point design in "RTL-like" designs?
  133. Standardized internal module bus
  134. ethernet checksum nightmare
  135. bits2real
  136. Visual IP Designer interresting new EDA tool
  137. FPSLIC vs Xilinx
  138. KO mafia ! Global Democracy TRIVOLUZIONE ARTSENU COLD FUSION W post OPEC
  139. undeclared identifier error message but all libraries are declaredand added (precision)
  140. After Place and Route
  141. Bitstream programming
  142. any particular things which need to be avoided?
  143. Opencore Wishbone I2C Application
  144. DC timing violation, what to do first?
  145. error in code / ALU / calculator
  146. Re: [XST 8.2.3] DSP48 inference multiply/add
  147. iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
  148. signal spy
  149. modulo of any number
  150. Xilinx FIFO CoreGen: Datacount goes to zero upon full flag
  151. Verilog code for MD5 algorithm
  152. Help Needed!!!
  153. New User Help SynaptiCad
  154. ModelSim ACTEL 6.1b help
  155. Various FPGAs
  156. VHDL design for combinational lock
  157. Use Multi-cycle Path or Pipeline?
  158. ALLEGRO PCB ROUTER AND ORCAD CIS, IAR Embedded.Workbench, Mentor Graphics, Tornado, VxWorks, Wind River, ARM, ArmCAD, National Instruments ( N.I. ) programs
  159. Ambiguous reference to type `UNSIGNED' - How to deal with this issue?
  160. Is this Multi-Cycle Path ?
  161. inserting text into a video stream (from a pre-existing video source)
  162. Interlock and stall in CPU design?
  163. Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ from a driving signal of its?
  164. Custom indentation in Emacs Vhdl-mode
  165. Signal wont get out of U-state ????
  166. Command log in MODELSIM
  167. Illegal concurrent statement
  168. What FSM should I use ?
  169. Is this Code synthesizable and any suggestions
  170. edif format
  171. PID Controllers Questions
  172. Registered?
  173. vhdl design verified according to DO-254
  174. FIFO depth?
  175. Variable vs. Signal on indexing
  176. sinusoidal wave & VHDL
  177. benchmarks for vhdl codes
  178. Xilinx A Couple of questions
  179. synthesis equivalent statement/code/suggestions ?
  180. Cool Runner VCCAux Question
  181. Different Modelsim versions disagree in same backannotation!
  182. set different constants for simulation than for synthesis (preprocessor?)
  183. IMPLEMENTING ALU WITH OVERFLOW DETECTION ABILITY
  184. Birth date for VHDL 87 ?
  185. Petri Networks - dividers of N
  186. vhdl simulator speed test
  187. avoiding division
  188. DATA-FORWARDING IN A RISC PIPELINE
  189. Weird Modelsim warning while running backannotation
  190. clock domain switch fast to slow
  191. Good hardware design code re-use strategies, reference book
  192. NIOS II Application startup issues
  193. CFP: CEC2007 Special session on: Evolutionary Computation for EDA
  194. C-Systemc-VHDL problem in Modelsim
  195. video buffering scheme, nonsequential access (no spatial locality)
  196. How to do the shift bit operation in Array
  197. Call for Papers: WORLDCOMP'07: conferences in computer science & computer engineering, USA
  198. regarding arrays..........
  199. sensitivity list
  200. State machine with control outputs
  201. Datapath design problem?
  202. VHDL-200x Fixed_pkg Problems
  203. how do you code this?
  204. Problem with I/O files.
  205. 32 bit floating point multiplier
  206. Xilinx floating-pt IP not working?
  207. Unconstrained array ports - Good or Bad?
  208. Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
  209. Electrical gigabit transmission ?
  210. converting ahdl to vhdl
  211. (vhdl-mode) Current context
  212. How to disable "_i" insertion on signals in emacs VHDL mode
  213. Numeric variable type
  214. Keypad vhdl code stuff
  215. Having trouble with my FIR filter, help much appreciated.
  216. problem with sll
  217. Wrong IDCODE
  218. Convert Real number to Std_logic_vector
  219. Bidirectional bus and virtual pins
  220. ABout Matrix transpose
  221. Another Verilog to VHDL converter request
  222. simulator Error
  223. [Q]: Is Digilent still in business ???
  224. referencing externally declared signals in a package
  225. verilog testbench fot vhdl ams
  226. Including Verilog parameter file in VHDL design
  227. Quartus FFT IP problem
  228. Quartus FFT IP problem
  229. Xilinx Error
  230. URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENERATION ON FPGA.....
  231. HCM / LCM signalling
  232. Pulse stretching
  233. Counter simulation proper but giving trouble in DFT
  234. Counter simulation proper but giving trouble in DFT
  235. Counter simulation proper but giving trouble in DFT
  236. RFC: does this make any sense?
  237. urgently needed
  238. counters in fsm
  239. random generator in hardware
  240. Project on Implementaion of PDA( personal digital assistant)
  241. Quartus FFT IP output problem
  242. Quartus FFT IP output problem
  243. Specify bit position in array of vectors
  244. Building Coaxial transmission line on PCB?
  245. SONET deframer design ....
  246. Last Call for Papers: 2007 International Conference on Modeling, Simulation and Visualization Methods (MSV'07), June 25-28, 2007, USA
  247. How to mix verilog and vhdl files in one core
  248. ramp generator
  249. CRC calculation
  250. dynamic memory allocation for images in a test bench