View Full Version : VHDL

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  1. Beginners VHDL:
  2. reading from files
  3. Xilinx WebPack 8.1i "desoptimization"
  4. isolating cells, clamps
  5. inout problem
  6. SPI Problem
  7. SPP for Digilab
  8. integer'image string width
  9. FPGA-programmers and VHDL on OS-X?
  10. UART with fractional baudrate generator ? Or fractional baudrate generator alone
  11. need a help in vhdl code developing
  12. basic VHDL question
  13. How to clarify algorithm of hardware(HDL)?
  14. Boolean as port type
  15. Generate state with non-static range?
  16. ram model
  17. How to convert from netlist to Boolean expression - PLEASE HELP
  18. array
  19. different variable in generate statement
  20. Map net into BRAM
  21. Is there anything fundamentally wrong with this code?
  22. Are there any Modelsim hooks to allow testbench code to figure out procedure call stack?
  23. MCU clock divider vs. VHDL divider
  24. State machine glitch
  25. Problem with operation
  26. Problem with shift operation
  27. twos complement data
  28. Fake vcc and gnd
  29. Non power of 2 natural counter - neat alternatives to mod operator?
  30. how to write a conditional assignment over generic or constant?
  31. Package texio - writeline and deallocate
  32. vhdl cpu emulator (any interest?)
  33. character to std_logic value
  34. character to std_logic value
  35. FSM for parallel port
  36. VERIFICATION TESTPLAN
  37. About counter in VHDL
  38. What is the best way to clock data in on one clock edge and out on another?
  39. Interesting XST warning
  40. Modelsim Simulation
  41. newbie problem with Xilinx tutorial
  42. real to time
  43. std_logic resolution
  44. CCITT CRC X1021 parallel calc
  45. for language experts: generic lower in list may reference generics higher in list
  46. please help me out
  47. Combinational feedback loops
  48. vhdl 200x status?
  49. Verilog book recommendation
  50. [AHDL]
  51. VHDL Generics problem when simulating SDF with Scirocco
  52. Converting std_logic_vector to integer
  53. optimizing my design
  54. The assign statement in verilog doesnt generate a module in design architect
  55. for language experts: RANGE TYPE
  56. RAM simulation (HM6116P)
  57. fpga programming
  58. stdio_h.vhd and 0x prefixes
  59. Problem :(
  60. Records & Synthesis
  61. VHDL integer signal in tri-state
  62. DRAM controller???
  63. Needed good website on DES algorithm
  64. best way to code an adder
  65. VHDL project required
  66. VHDL Variables Question
  67. Mapping a std_bit_vector to a record
  68. help on coding pls~
  69. Failing paths
  70. Re: Cordic-based Sine Computer in MyHDL
  71. vhdl coding and glitches that my result
  72. DATAIO ABEL
  73. primetime
  74. Design with IP-Cores on different FPGAs
  75. Shift Register Problem
  76. Modeling a quantiser in VHDL (synthesisable circuit)
  77. for language experts: Constants defined in an entity visible in all deeper inner entities
  78. CORDIC Bibliography Site: new life
  79. Question to resolved signals, transport delay
  80. The differences between behaviors of 'std_logic_vector' and 'unsigned'
  81. problem with data flow modelling
  82. A constant value of 0 in block
  83. optimization of vhdl code
  84. A problem with crc-32 check
  85. function(help!)
  86. function call(help)
  87. nesting counters
  88. nesting counters
  89. problem in optimization of vhdl code
  90. 4 level to 2 level round robin arbiter
  91. Cross clock domain control signal convey
  92. floating ^point data
  93. Xilinx vhdl counter recognised as register
  94. How to simulate the connection of to bidir ports ?
  95. Easy way to define lots of zeroes
  96. Logical gates tester
  97. USART help
  98. trunc in verilog
  99. uart.vhd compile problems
  100. Verification by Non-HDL(C++/Java)??
  101. HDL AUTHOR and SLL problem!
  102. computer bus technology discuss community
  103. Arbiter for the wishbone bus
  104. Bit reversal and IRC
  105. Package monitor signals from FAQ
  106. Quartus v6.0 problem
  107. simulation working , synthesis causing problems
  108. How to create a FIFO memory device
  109. difference of variable and signal
  110. To_stdlogicvector
  111. Competent VHDL Simulators?
  112. VHDL--usage of WAIT statement in PROCESS
  113. Free VHDL Simulator(s) ..?
  114. ISE Webpack 8.1: Problems simulating a testbench waveform
  115. error
  116. how to make a simple "gateway"?
  117. Problem with JTAG_SIM_VIRTEX4
  118. variable scope
  119. synthesis of comparison operators
  120. numeric_std vs std_logic_arith/unsigned?
  121. Don't know what to do: std_logic_1164.v93 has changed...
  122. Std_Logic signal assignment snafu
  123. "Generics" in VHDL Package
  124. Assigning different bits of the same signal
  125. Help!!!
  126. how to convert real type to std_logic_vector ?
  127. t flip flops
  128. t flip flops
  129. Cyclone II PCI & pin swapping
  130. Bi directional data signal in cpu
  131. Chipmunk/diglog
  132. a little C code to VHDL
  133. error with REM of numeric_std
  134. frequency divider
  135. piecewise function
  136. efficient therm-2-bin algorithm
  137. ANYONE HAS A VHDL CODE EXAMPLE FOR A PHERIPHERAL DEVICE INTERFACE DESIGN to a PC PARALLEL PORT (ECP MODE)
  138. Required VHDL codes
  139. 8 bit into 256 bit shift register
  140. unsupported types
  141. XST Warning 790: What does it mean?
  142. file_open_status
  143. Clock Signal in VHDL
  144. optimization of vhdl code
  145. Paradigms in implementation of counters
  146. array of array
  147. generics
  148. problems with FSMs
  149. About Generic
  150. VHDL 7 segment diaplay using ram & Rom function
  151. using FIX_STD
  152. GHDL for windows
  153. error with synthesis
  154. problem with variable values
  155. when will vhdl-200x be released ?
  156. Making library for FPHDL
  157. fsm
  158. Coding style
  159. probleme in code
  160. coding help
  161. AHB Slave Interface SPLIT requirement
  162. Declaring constants
  163. seagate hard disk driver problem
  164. newbie: integer to bit_vector
  165. Port Map Array
  166. Tornado, VxWorks, Wind River, ARM, ArmCAD, National Instruments ( N.I. ) programs 2005 -, CDs
  167. EDA, PCB, Mentor Graphics programs 2006 - , programs,
  168. Math Solving, and Statistics Programs
  169. How many of the old reference sites are still around?
  170. VHDL File-based CPU Emulator : Available
  171. How to debug suspected driver conflict?
  172. Howto Create a library from vhdl source with design compiler ?
  173. are this two equivalent?
  174. how to see signal in labrary in Simvision?
  175. [DC ASIC] Why more area == good timing?
  176. rslatch model
  177. common dataflow tree for verilog and vhdl
  178. INOUT std_logic problem in ModelSim
  179. 8 bit binary to 2 digit BCD
  180. Address Decoding Logic
  181. Address Decoding Logic
  182. control circuit for a bus
  183. control circuit for a bus
  184. VHDL Source Code Formatter
  185. Is it possible to run Verilog and VHDL combined
  186. Describing pipelined hardware
  187. ModelSim, controlling waveform display
  188. Quatrus II
  189. VHDL-200x and Object-Oriented Hardware design
  190. bit vector to std_logic conversion query
  191. Error: (vcom-11) Could not find work.const
  192. design querres
  193. flag handling
  194. Running two state machines with same clock.
  195. The corresponding Actel library of the Xilinx UNISIM
  196. Call for Participation: WORLDCOMP'06 (Computer Science & Computer Engineering), June 26-29, 2006, Las Vegas, USA
  197. Good free or paid merge software that edits two similar files?
  198. The 3rd International Electronics Design Contest for Students
  199. Arrays in Port
  200. Requesting for an Actel library
  201. what's wrong with this piece of code
  202. Confusion centered around the falling_edge
  203. limitations on xilinx webpack
  204. bus copying....
  205. Help: Design Compiler does not instantiate Asic's Library's FullAdder
  206. How to get lowest price for a ModelSim license?
  207. Conditional Generates
  208. How to overide ieee.std_logic_1164.all
  209. FIFO depth and code
  210. Binary to thermometric algorithm
  211. ANNC: VHDL Coding for FPGA Webcast
  212. Test
  213. Xilinx XST Error
  214. vhdl generate related
  215. Multiplexer
  216. CPLD ASIC?
  217. Second argument of write must have a constant value.
  218. open inputs and Unisim libraries
  219. Traffic light
  220. alternate synchronous process template
  221. Automatic VHDL Generating
  222. sequence generator
  223. Traffic light complete!
  224. Tcl DC Mode for Emacs
  225. latch warning...
  226. VITERBI INFO
  227. Newbie question about Wait for X and ModelSim
  228. Delay Counter
  229. Floppy to FPGA?
  230. Clocking inside an overloaded function
  231. Compilation of XilinxCoreLib with ghdl
  232. Nice, categorised reference for VHDL functions
  233. Arbitrary Clock Frequencies From Base Clock
  234. model pmos and nmos in VHDL
  235. Tutorials for Processor Designs
  236. problems with generate statement
  237. Counter Issue on FPGA and CPLD
  238. Xilinx ISE 8.1i Trouble
  239. CASE statement & LOOP
  240. vital question
  241. Modelsim and hex format file
  242. NC sim error with mixed mode
  243. I wait all your reponses and thoughts : FPGA Projects
  244. Problems with modelsim and conditional generate statement
  245. Array indexing problem: "Data corruption (ListDelShift) - Bad Index"
  246. Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem
  247. testbench question
  248. BPSK on VHDL (warning - VHDL newbie)
  249. string to std_logic_vector
  250. VHDL-200x fixed_pkg synthesis warnings