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- Including Verilog parameter file in VHDL design
- verilog testbench fot vhdl ams
- referencing externally declared signals in a package
- [Q]: Is Digilent still in business ???
- simulator Error
- Another Verilog to VHDL converter request
- ABout Matrix transpose
- Bidirectional bus and virtual pins
- Convert Real number to Std_logic_vector
- Wrong IDCODE
- problem with sll
- Having trouble with my FIR filter, help much appreciated.
- Keypad vhdl code stuff
- Numeric variable type
- How to disable "_i" insertion on signals in emacs VHDL mode
- (vhdl-mode) Current context
- converting ahdl to vhdl
- Electrical gigabit transmission ?
- Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
- Unconstrained array ports - Good or Bad?
- Xilinx floating-pt IP not working?
- 32 bit floating point multiplier
- Problem with I/O files.
- how do you code this?
- VHDL-200x Fixed_pkg Problems
- Datapath design problem?
- State machine with control outputs
- sensitivity list
- regarding arrays..........
- Call for Papers: WORLDCOMP'07: conferences in computer science & computer engineering, USA
- How to do the shift bit operation in Array
- video buffering scheme, nonsequential access (no spatial locality)
- C-Systemc-VHDL problem in Modelsim
- CFP: CEC2007 Special session on: Evolutionary Computation for EDA
- NIOS II Application startup issues
- Good hardware design code re-use strategies, reference book
- clock domain switch fast to slow
- Weird Modelsim warning while running backannotation
- DATA-FORWARDING IN A RISC PIPELINE
- avoiding division
- vhdl simulator speed test
- Petri Networks - dividers of N
- Birth date for VHDL 87 ?
- IMPLEMENTING ALU WITH OVERFLOW DETECTION ABILITY
- set different constants for simulation than for synthesis (preprocessor?)
- Different Modelsim versions disagree in same backannotation!
- Cool Runner VCCAux Question
- synthesis equivalent statement/code/suggestions ?
- Xilinx A Couple of questions
- benchmarks for vhdl codes
- sinusoidal wave & VHDL
- Variable vs. Signal on indexing
- FIFO depth?
- vhdl design verified according to DO-254
- Registered?
- PID Controllers Questions
- edif format
- Is this Code synthesizable and any suggestions
- What FSM should I use ?
- Illegal concurrent statement
- Command log in MODELSIM
- Signal wont get out of U-state ????
- Custom indentation in Emacs Vhdl-mode
- Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ from a driving signal of its?
- Interlock and stall in CPU design?
- inserting text into a video stream (from a pre-existing video source)
- Is this Multi-Cycle Path ?
- Ambiguous reference to type `UNSIGNED' - How to deal with this issue?
- ALLEGRO PCB ROUTER AND ORCAD CIS, IAR Embedded.Workbench, Mentor Graphics, Tornado, VxWorks, Wind River, ARM, ArmCAD, National Instruments ( N.I. ) programs
- Use Multi-cycle Path or Pipeline?
- VHDL design for combinational lock
- Various FPGAs
- ModelSim ACTEL 6.1b help
- New User Help SynaptiCad
- Help Needed!!!
- Verilog code for MD5 algorithm
- Xilinx FIFO CoreGen: Datacount goes to zero upon full flag
- modulo of any number
- signal spy
- iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
- Re: [XST 8.2.3] DSP48 inference multiply/add
- error in code / ALU / calculator
- DC timing violation, what to do first?
- Opencore Wishbone I2C Application
- any particular things which need to be avoided?
- Bitstream programming
- After Place and Route
- undeclared identifier error message but all libraries are declaredand added (precision)
- KO mafia ! Global Democracy TRIVOLUZIONE ARTSENU COLD FUSION W post OPEC
- FPSLIC vs Xilinx
- Visual IP Designer interresting new EDA tool
- bits2real
- ethernet checksum nightmare
- Standardized internal module bus
- Does VHDL accept floating point design in "RTL-like" designs?
- A Sorting Circuit in Digital Logic Design
- Matlab (.m) to VHDL
- Embedded Development Tools
- last_value
- Tracing UNKNOWN drivers
- Tracing UNKNOWN drivers
- Warning message
- parser VHDL to DOT (graphviz)
- A question about variable thing
- unexplainable Problem on Spartan 3
- function and its hardware?
- connection
- OT : Bug/Issue tracking systems
- hi friends, pls guide me to find ASIC Verification Engineers with VERA or Specman expereince
- Xilinx .npl to .ise can't convert
- Merging arrays in Modelsim
- Lcd Block Diagram - Vhdl - On Fpga.. help!
- multiplying std logic vectors
- lib & package
- regards NULL character reading
- regards NULL character reading
- Quartus II compilation too slow for RAM design
- GUI Based vs. Manual Instantiation of Components
- gate logic synthesis
- Synopsys SMP3 Reference Model
- DDR2 VHDL model
- Fpga
- Mapping signals to components
- VHDL 2 VERILOG CONVERTER FOR AHB
- conv_std_logic_vector
- Objects list at ModelSim
- Simple question about if statemets
- Book and a starter kit
- ModelSim SE 6.1f : code coverage database merge problem
- problem in vhdl code with a one clock delay
- computer vision projects for open cores
- Urgent Requirement for ASIC Verification Engineers in CA
- Urgent Requirement for ASIC Verification Engineers in CA
- FFT on Virtex-II Pro (how to download .dat file?)
- FFT on Virtex II Pro (how to download .dat file?)
- Partial Aggregate Assignment
- Synchronizing two different clocks
- CMI Coder/Decoder
- More Configuration Problems
- Graphics engine IP
- Divison Operation
- Variable Input file length
- how can I set outputs high on startup?
- numeric_std omissions
- Call For Papers/Sessions: WORLDCOMP'07: multiple int'l. conferences in computer science & computer engineering, USA
- viterbi decoder
- Global Clock
- The best way to implement this non-power-of-two modulo-like function on a limited subtype?
- multiplier
- viterbi implementation on actel fpga
- problem in optimization of top level
- Data structures and signals and stuff.
- Reconfigurable PLL
- Integer arithmetic
- FFT in AHDL
- Matlab and VHDL
- How to calculate amplitude and phase of a digital/analog signal in VHDL?
- procedure overloading vs. ?
- Netlist simulation
- Comparing counters in two different clock domains
- How to describe this block diagram in VHDL?
- VHDL vs. System Generator, et al.
- Help with assert statement
- How to meet timing constraints in an FPGA
- inverse function, how?
- junk/garbage posts
- are wombats good?
- where are wombats?
- problems with verilog SDRAM models
- Question about conditional generate
- Question about conditional generate
- Synchronizer theory and question
- Saving results from a simulation
- Modelsim AE / multiple waveform windows
- Timing constraints in an FPGA
- Counter Glitches Question
- Verilog Ref Book
- simple state machine
- Modelsim: have the compile report in the transcript window ?
- AMD/Spansion FLASH problem
- Problem with Fix_std
- What's Nonpipelined bus mean?
- XC2S30 with display VQC10
- LOAD on asynchronous RESET
- cosimulate VHDL with Simulink help need
- MIG tool DDR1 interface !
- Error: VHDL Use Clause error at quartustest.vhd(6): design library "IEEE" does not contain primary unit "std_logic_textio"
- Creating a delay with VHDL without using wait (n00b)
- ADC and DAC Converters VHDL model
- Data checking
- Data checking
- change initial value of state machine
- I2C "READ" Setup/Hold Requirement
- Post Synthesis VHDL
- i need a help to solve a problem in VHDL
- opencores projects
- How to find the ABS of std_logic_vector
- Having access to a VHDL "signal" using ModelSim
- Having access to a VHDL "signal" using ModelSim
- Sign extension
- ISE Bug?
- Bi-Directional Bus inside Spartan 3
- GOOD REFFERENCE BOOK NEEDED
- Circular dependency problem
- VHDL to Verilog Converter
- Modelsim Assert
- reading files help
- Changing files
- how to add a new library in xilinx.
- signed multiplication
- conv_integer simulation whining in ISE
- Problems with Opencores' I2C "READ" function
- 'event attribute & modelsim 6.0 problem
- VHDL Help with Spartan 3
- Problems with GHDL and GTKWave
- Syntax help
- using files for testbench
- Is there a way to combine verilog and vhdl?
- MODULUS operator
- help please
- FFT in VHDL (or Verilog) Tutorial
- Xilinx-altera-problem
- two-dimensional arrays cannot be simulated
- Warning ==> Latches
- Carry Save Adder (CSA) Verilog code
- Delta Delays
- PLL and another design together
- Simulate VHDL core model with C program
- VHDL JUST FOR ENGINEERS
- Re: Adding internal signals in Modelsim
- VHDL description of an array structure
- VHDL simulator on linux
- Can someone please help?
- Implementing VHDL with FPGA
- constant bitrate approach with lossless data compression on an FPGA
- STD_U/ LOGIC ???
- data enable on a FF
- First Posting
- driving bidirectional std_ulogic_vector
- Xst:1895 Error
- floating point arithemetic on fpga
- Dividing by 48
- std_logic_vector to unsigned conversion
- FPGA design
- WORLDCOMP'07: Call For Papers/Sessions--multiple int'l. conferences in computer science & computer engineering, USA
- "casting" bits to bits?
- how to set the frequency of clock of FPGA
- How can I load my program into the memory of a Spartan 3 board
- Modelsim problem - mixed VHDL,Verilog & VHO
- MODEL SIM 6.0E
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