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  1. Including Verilog parameter file in VHDL design
  2. verilog testbench fot vhdl ams
  3. referencing externally declared signals in a package
  4. [Q]: Is Digilent still in business ???
  5. simulator Error
  6. Another Verilog to VHDL converter request
  7. ABout Matrix transpose
  8. Bidirectional bus and virtual pins
  9. Convert Real number to Std_logic_vector
  10. Wrong IDCODE
  11. problem with sll
  12. Having trouble with my FIR filter, help much appreciated.
  13. Keypad vhdl code stuff
  14. Numeric variable type
  15. How to disable "_i" insertion on signals in emacs VHDL mode
  16. (vhdl-mode) Current context
  17. converting ahdl to vhdl
  18. Electrical gigabit transmission ?
  19. Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
  20. Unconstrained array ports - Good or Bad?
  21. Xilinx floating-pt IP not working?
  22. 32 bit floating point multiplier
  23. Problem with I/O files.
  24. how do you code this?
  25. VHDL-200x Fixed_pkg Problems
  26. Datapath design problem?
  27. State machine with control outputs
  28. sensitivity list
  29. regarding arrays..........
  30. Call for Papers: WORLDCOMP'07: conferences in computer science & computer engineering, USA
  31. How to do the shift bit operation in Array
  32. video buffering scheme, nonsequential access (no spatial locality)
  33. C-Systemc-VHDL problem in Modelsim
  34. CFP: CEC2007 Special session on: Evolutionary Computation for EDA
  35. NIOS II Application startup issues
  36. Good hardware design code re-use strategies, reference book
  37. clock domain switch fast to slow
  38. Weird Modelsim warning while running backannotation
  39. DATA-FORWARDING IN A RISC PIPELINE
  40. avoiding division
  41. vhdl simulator speed test
  42. Petri Networks - dividers of N
  43. Birth date for VHDL 87 ?
  44. IMPLEMENTING ALU WITH OVERFLOW DETECTION ABILITY
  45. set different constants for simulation than for synthesis (preprocessor?)
  46. Different Modelsim versions disagree in same backannotation!
  47. Cool Runner VCCAux Question
  48. synthesis equivalent statement/code/suggestions ?
  49. Xilinx A Couple of questions
  50. benchmarks for vhdl codes
  51. sinusoidal wave & VHDL
  52. Variable vs. Signal on indexing
  53. FIFO depth?
  54. vhdl design verified according to DO-254
  55. Registered?
  56. PID Controllers Questions
  57. edif format
  58. Is this Code synthesizable and any suggestions
  59. What FSM should I use ?
  60. Illegal concurrent statement
  61. Command log in MODELSIM
  62. Signal wont get out of U-state ????
  63. Custom indentation in Emacs Vhdl-mode
  64. Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ from a driving signal of its?
  65. Interlock and stall in CPU design?
  66. inserting text into a video stream (from a pre-existing video source)
  67. Is this Multi-Cycle Path ?
  68. Ambiguous reference to type `UNSIGNED' - How to deal with this issue?
  69. ALLEGRO PCB ROUTER AND ORCAD CIS, IAR Embedded.Workbench, Mentor Graphics, Tornado, VxWorks, Wind River, ARM, ArmCAD, National Instruments ( N.I. ) programs
  70. Use Multi-cycle Path or Pipeline?
  71. VHDL design for combinational lock
  72. Various FPGAs
  73. ModelSim ACTEL 6.1b help
  74. New User Help SynaptiCad
  75. Help Needed!!!
  76. Verilog code for MD5 algorithm
  77. Xilinx FIFO CoreGen: Datacount goes to zero upon full flag
  78. modulo of any number
  79. signal spy
  80. iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
  81. Re: [XST 8.2.3] DSP48 inference multiply/add
  82. error in code / ALU / calculator
  83. DC timing violation, what to do first?
  84. Opencore Wishbone I2C Application
  85. any particular things which need to be avoided?
  86. Bitstream programming
  87. After Place and Route
  88. undeclared identifier error message but all libraries are declaredand added (precision)
  89. KO mafia ! Global Democracy TRIVOLUZIONE ARTSENU COLD FUSION W post OPEC
  90. FPSLIC vs Xilinx
  91. Visual IP Designer interresting new EDA tool
  92. bits2real
  93. ethernet checksum nightmare
  94. Standardized internal module bus
  95. Does VHDL accept floating point design in "RTL-like" designs?
  96. A Sorting Circuit in Digital Logic Design
  97. Matlab (.m) to VHDL
  98. Embedded Development Tools
  99. last_value
  100. Tracing UNKNOWN drivers
  101. Tracing UNKNOWN drivers
  102. Warning message
  103. parser VHDL to DOT (graphviz)
  104. A question about variable thing
  105. unexplainable Problem on Spartan 3
  106. function and its hardware?
  107. connection
  108. OT : Bug/Issue tracking systems
  109. hi friends, pls guide me to find ASIC Verification Engineers with VERA or Specman expereince
  110. Xilinx .npl to .ise can't convert
  111. Merging arrays in Modelsim
  112. Lcd Block Diagram - Vhdl - On Fpga.. help!
  113. multiplying std logic vectors
  114. lib & package
  115. regards NULL character reading
  116. regards NULL character reading
  117. Quartus II compilation too slow for RAM design
  118. GUI Based vs. Manual Instantiation of Components
  119. gate logic synthesis
  120. Synopsys SMP3 Reference Model
  121. DDR2 VHDL model
  122. Fpga
  123. Mapping signals to components
  124. VHDL 2 VERILOG CONVERTER FOR AHB
  125. conv_std_logic_vector
  126. Objects list at ModelSim
  127. Simple question about if statemets
  128. Book and a starter kit
  129. ModelSim SE 6.1f : code coverage database merge problem
  130. problem in vhdl code with a one clock delay
  131. computer vision projects for open cores
  132. Urgent Requirement for ASIC Verification Engineers in CA
  133. Urgent Requirement for ASIC Verification Engineers in CA
  134. FFT on Virtex-II Pro (how to download .dat file?)
  135. FFT on Virtex II Pro (how to download .dat file?)
  136. Partial Aggregate Assignment
  137. Synchronizing two different clocks
  138. CMI Coder/Decoder
  139. More Configuration Problems
  140. Graphics engine IP
  141. Divison Operation
  142. Variable Input file length
  143. how can I set outputs high on startup?
  144. numeric_std omissions
  145. Call For Papers/Sessions: WORLDCOMP'07: multiple int'l. conferences in computer science & computer engineering, USA
  146. viterbi decoder
  147. Global Clock
  148. The best way to implement this non-power-of-two modulo-like function on a limited subtype?
  149. multiplier
  150. viterbi implementation on actel fpga
  151. problem in optimization of top level
  152. Data structures and signals and stuff.
  153. Reconfigurable PLL
  154. Integer arithmetic
  155. FFT in AHDL
  156. Matlab and VHDL
  157. How to calculate amplitude and phase of a digital/analog signal in VHDL?
  158. procedure overloading vs. ?
  159. Netlist simulation
  160. Comparing counters in two different clock domains
  161. How to describe this block diagram in VHDL?
  162. VHDL vs. System Generator, et al.
  163. Help with assert statement
  164. How to meet timing constraints in an FPGA
  165. inverse function, how?
  166. junk/garbage posts
  167. are wombats good?
  168. where are wombats?
  169. problems with verilog SDRAM models
  170. Question about conditional generate
  171. Question about conditional generate
  172. Synchronizer theory and question
  173. Saving results from a simulation
  174. Modelsim AE / multiple waveform windows
  175. Timing constraints in an FPGA
  176. Counter Glitches Question
  177. Verilog Ref Book
  178. simple state machine
  179. Modelsim: have the compile report in the transcript window ?
  180. AMD/Spansion FLASH problem
  181. Problem with Fix_std
  182. What's Nonpipelined bus mean?
  183. XC2S30 with display VQC10
  184. LOAD on asynchronous RESET
  185. cosimulate VHDL with Simulink help need
  186. MIG tool DDR1 interface !
  187. Error: VHDL Use Clause error at quartustest.vhd(6): design library "IEEE" does not contain primary unit "std_logic_textio"
  188. Creating a delay with VHDL without using wait (n00b)
  189. ADC and DAC Converters VHDL model
  190. Data checking
  191. Data checking
  192. change initial value of state machine
  193. I2C "READ" Setup/Hold Requirement
  194. Post Synthesis VHDL
  195. i need a help to solve a problem in VHDL
  196. opencores projects
  197. How to find the ABS of std_logic_vector
  198. Having access to a VHDL "signal" using ModelSim
  199. Having access to a VHDL "signal" using ModelSim
  200. Sign extension
  201. ISE Bug?
  202. Bi-Directional Bus inside Spartan 3
  203. GOOD REFFERENCE BOOK NEEDED
  204. Circular dependency problem
  205. VHDL to Verilog Converter
  206. Modelsim Assert
  207. reading files help
  208. Changing files
  209. how to add a new library in xilinx.
  210. signed multiplication
  211. conv_integer simulation whining in ISE
  212. Problems with Opencores' I2C "READ" function
  213. 'event attribute & modelsim 6.0 problem
  214. VHDL Help with Spartan 3
  215. Problems with GHDL and GTKWave
  216. Syntax help
  217. using files for testbench
  218. Is there a way to combine verilog and vhdl?
  219. MODULUS operator
  220. help please
  221. FFT in VHDL (or Verilog) Tutorial
  222. Xilinx-altera-problem
  223. two-dimensional arrays cannot be simulated
  224. Warning ==> Latches
  225. Carry Save Adder (CSA) Verilog code
  226. Delta Delays
  227. PLL and another design together
  228. Simulate VHDL core model with C program
  229. VHDL JUST FOR ENGINEERS
  230. Re: Adding internal signals in Modelsim
  231. VHDL description of an array structure
  232. VHDL simulator on linux
  233. Can someone please help?
  234. Implementing VHDL with FPGA
  235. constant bitrate approach with lossless data compression on an FPGA
  236. STD_U/ LOGIC ???
  237. data enable on a FF
  238. First Posting
  239. driving bidirectional std_ulogic_vector
  240. Xst:1895 Error
  241. floating point arithemetic on fpga
  242. Dividing by 48
  243. std_logic_vector to unsigned conversion
  244. FPGA design
  245. WORLDCOMP'07: Call For Papers/Sessions--multiple int'l. conferences in computer science & computer engineering, USA
  246. "casting" bits to bits?
  247. how to set the frequency of clock of FPGA
  248. How can I load my program into the memory of a Spartan 3 board
  249. Modelsim problem - mixed VHDL,Verilog & VHO
  250. MODEL SIM 6.0E