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  1. 64 bit matrix multplication
  2. "High VIOLATION ON I WITH RESPECT TO CLK"
  3. Cannot transmit correct result consecutively
  4. FMF Spansion model & timing
  5. need code
  6. generate statement inside a process (conditional variable declaration)
  7. Help with typecasting requested
  8. ANN: Tyd-IP Code Generator V3.1 released
  9. Post-Route Simulation does not give output for the first clock cycle
  10. How can I avoid multiple execution when handshaking operations?
  11. type/subtype definition in entity
  12. ISE Simulator error with package
  13. Presto Synopsys Compiler
  14. PCB functional modeling
  15. if/elsif problem
  16. Experience of IEEE.Float_Pkg?
  17. Signal zaehl cannot be synthesized
  18. Use BRam and DRam on FPGA's Xilinx
  19. Call for Papers: WORLDCOMP'07, Las Vegas, June 25-28, Conferences in Computer Science, Computer Engineering, and Applied Computing
  20. vhdl code for baugh wooley multiplier
  21. 4 bit adder with overflow check
  22. inferring latch
  23. Script to Expand Buses and Ports?
  24. simulator
  25. problem with code for random number generation
  26. TCP/IP implementation in Virtex 4
  27. dct/IDCT IN VHDL
  28. HOW TO USE A FILE WITH VHDL?
  29. HOW TO USE A FILE WITH VHDL?
  30. procedure inside package body and modelsim error
  31. Not able to figure out the error.. Need help
  32. Warning of Xst:2677
  33. Question about Ben Cohen's switch model
  34. One of my signals not initialising
  35. code for synchronous
  36. Query in 32 bit Parallel CRC...urgent
  37. Questions on VHDL
  38. Available: Detailed RISC CPU IP Core Design Documentation
  39. JTAG Tap Master (was: TI Tap Controller std8980)
  40. Random Generator for Testbench
  41. Fractions
  42. Weird stuff in VHDL
  43. p88
  44. VHDL testbench enhancement proposals for OO and randomization
  45. Generic entities in package
  46. Command Decoder?
  47. require vhdl code
  48. Function has Sim vs. Syth Non-Equivalence
  49. serial out
  50. storing values in a reg
  51. Suppressing multiple driver warning where not needed
  52. Interfacing the DAC0808 to FPGA
  53. TI Tap Controller std8980
  54. swapping bits in a byte
  55. VHDL-AMS Q'ltf
  56. combitorial loop
  57. Does anyone know where I can find a VHDL code for a slave printer interface in EPP mode?
  58. RFC: VHDL testbench enhancements
  59. Synthesis and FILE I/O?!
  60. Implementing a communication protocol for data transfer over TCP on an FPGA
  61. Lines of code being ignored in my process constructs
  62. IN the PSL...
  63. inferred ram with initial values
  64. init
  65. doubt in power calculation
  66. Does anyone know where I can find a VHDL code for a slave printer interface in EPP mode?
  67. Thomas & Moorby Verilog Reference: $41
  68. Does anyone know where I can find a VHDL code for a slave printer interface in EPP mode?
  69. Does anyone know where I can find a VHDL code for a slave printer interface in EPP mode?
  70. Follow-up on text processing functions
  71. EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07
  72. Some text processing questions
  73. RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
  74. Linear interpolation for image upscaling
  75. Async clear plus edge triggered Set/Clr ?
  76. Need help with sequential fault simulation in Tetramax!!!
  77. LFSR code
  78. Using default value of a generic in VHDL
  79. ANNC: Tips for FPGA Timing Closure Webcast
  80. X=T * AT '
  81. Measure simulation time in VHDL.
  82. Open-source CPU-core for standard-cell ASIC?
  83. A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
  84. Identifier issue
  85. Coding complex VHDL testbenches
  86. VHDL port inout problem
  87. Xilinx Coregen (FFT): Unconected output pin/no driver
  88. Multiple wait statements inside one process
  89. new to VHDL: concurrent execution question
  90. Tying two wires together
  91. Xilinx multiplier core instantiation for Virtex4
  92. Question about conditional assignment
  93. Converting records from/to std_logic_vector
  94. VDC needs help with ESL/EDA Survey
  95. Why multiplex signals?
  96. req:dsip library for vhdl
  97. how to use noreduce
  98. how to read a video
  99. thinks
  100. thinks
  101. VHDL-2002 vs VHDL-93 vs VHDL-87?
  102. Resume ModelSim sim from wlf?
  103. multiple clock domains issues
  104. gated clock
  105. plz hel me to design edgedetector
  106. How to avoid 'unable to synthesize' errors
  107. Simulation IPprocessor and FPGA
  108. file read in Virtex II board
  109. bit_vector comparison
  110. VHDL Style
  111. Getting Latch when don't want.
  112. ISERDES serialize and deserialize - Data to width.
  113. VHDL help
  114. Vernier Interpolation
  115. VHDL scalar attribute syntax
  116. Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
  117. VHDL PLI
  118. What official function should I call to genertate a sum of products in VHDL
  119. altera Flex10k + I2C
  120. Quartus II v5.1 don't read a file
  121. std_logic_vector 64bits with data 8 bits
  122. constuire un bus 64bits avec des data 8bits
  123. Syetem time in VHDL?
  124. Need Help...on Modelsim..VHDL syntax? ASAP:)
  125. Expression sizing: VHDL vs. Verilog
  126. Xilinx Asynchronous FIFO
  127. DDR Why not
  128. Problem when output data with some interval
  129. picoBlaze Question
  130. dual ported RAM - different aspect ratio
  131. Double Clock Frequency
  132. VSim component not bound
  133. sum of array
  134. verilog strength equivalent in vhdl
  135. Sum of element array
  136. Sum of array
  137. Sum of array
  138. Fractional Divider
  139. Need help with file input..
  140. message no data on modelsim
  141. New VLSI Site with useful info
  142. New VLSI Site with useful info
  143. Problem with a Testbench and Modelsim
  144. New tool for verification IPcors [ACTEL & ALDEC]
  145. Indirect assignment.
  146. ModelSim Error : "Fatal error in Process determine_phase_shift" during post synthesis of Xilinx vhd
  147. process factorisation
  148. i need vhdl code for tristate logic and schmitt input trigger buffer
  149. calculate Y Y = A * X * At
  150. calculate Y Y = A * X * At
  151. Fixed and floating point test
  152. hai
  153. utf8 to utf16
  154. if and and vs if and,and
  155. unused signal
  156. VHDL-AMS photodiode
  157. Phase Locked Oscillator
  158. Up down counter with two clocks?
  159. Hardware Models?
  160. Error during place and route: CLK0_BUFG_INST is not placed
  161. Re: Multiple devices within one ISE project
  162. Current Verilog-to-VHDL Conversion
  163. How best do I implement routing boxes in RTL?
  164. Dual Edge Oversampling
  165. VHDL Types/Subtypes
  166. stepper motor controller VHDL
  167. regards delays
  168. sdf file
  169. link betwen signal vhdl bench and entity (quartus2&modelsim)
  170. double signal affectation
  171. module RGBtoYCrCb
  172. VHDL file IO (using file as variable)
  173. VHDL assign multiple concatenated signals
  174. Simple combinational circuit VHDL code
  175. VHDL test bench with quartus 2? How ?
  176. Reading and writing the file
  177. Reading and writing the file
  178. Writing hexadecimal to file
  179. memory element inference from variable
  180. help for "sll" shift left logical
  181. long/short sensitivity list
  182. A Very good VLSI chip design & development website
  183. VHDL and Latch
  184. VHDL Design Process for CMMI
  185. counter with different rates...
  186. LCD vhdl code
  187. vhdl code for multiplier in filters
  188. Necessity of clk'event in Process
  189. Difference between U, X and -
  190. help about operation :s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
  191. help about operation :s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
  192. VHDL language grammar
  193. VHDL - Code verification - links
  194. combinational logic in reference design
  195. looking for the source VHDL for Jpeg 2000!
  196. Looking for LFSR code
  197. Any VHDL designers in Western NC
  198. Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")
  199. about fifo architecture.
  200. want info on resolved signal....
  201. floating point divider
  202. list for me plz
  203. list for me plz
  204. verifying the c program
  205. Variable bus widths
  206. verilog to vhdl
  207. question on fifo depth...
  208. help for motion compensation
  209. Verilog guy has to learn VHDL, Books?
  210. unsigned to integer conversion
  211. port list order
  212. convert std_logic_vector_16 to std_logic_vector_32
  213. Call for Papers with Extended Deadline: WORLDCOMP'07 (June 25-28, 2007, Las Vegas, USA): conferences in computer science, computer engineering, and applied computing
  214. std_logic_vector Array Input
  215. Beginner question about slice and LUT
  216. Call for Papers (Extended Deadline): 2007 International Conference on Modeling, Simulation and Visualization Methods (MSV'07), June 25-28, 2007, USA
  217. fft help
  218. Naming conventions for signals, ports, components, instances?
  219. Computing the width of an unsigned variable from maximum value?
  220. Dual Edge
  221. whats wrong with this code???
  222. Asynchronous circuitry or mixed circuitry design possible ?
  223. needed basics of FIFO design and in writing test benches
  224. synthesizable
  225. Wait statement in a Process
  226. Exact synatx required...!
  227. dynamic memory allocation for images in a test bench
  228. CRC calculation
  229. ramp generator
  230. How to mix verilog and vhdl files in one core
  231. Last Call for Papers: 2007 International Conference on Modeling, Simulation and Visualization Methods (MSV'07), June 25-28, 2007, USA
  232. SONET deframer design ....
  233. Building Coaxial transmission line on PCB?
  234. Specify bit position in array of vectors
  235. Quartus FFT IP output problem
  236. Quartus FFT IP output problem
  237. Project on Implementaion of PDA( personal digital assistant)
  238. random generator in hardware
  239. counters in fsm
  240. urgently needed
  241. RFC: does this make any sense?
  242. Counter simulation proper but giving trouble in DFT
  243. Counter simulation proper but giving trouble in DFT
  244. Counter simulation proper but giving trouble in DFT
  245. Pulse stretching
  246. HCM / LCM signalling
  247. URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENERATION ON FPGA.....
  248. Xilinx Error
  249. Quartus FFT IP problem
  250. Quartus FFT IP problem