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- Query about tan inverse function
- number of bits needed
- error trying to simulate NCO form quartus in matlab
- VHDL vs. Verilog
- help with incrementors
- timing simulation problem
- timing simulation problem
- Multiple input Adder
- Using unregistered inputs in FSM
- Synchronizer doubts
- Synchronizer doubts
- Design is too large for the device! xc3s400
- [VHDL Beginner] About ressources used
- changes for synthesizable code
- VHDL question
- What is "ASIC turnkey service"?
- Question about shifting
- CRC Doubts
- Relocating - need advice
- need help in using VHPI
- Help in VHDL!!!
- n bit adder
- Count with specific bits of the counter
- Warning in Modelsim - vector truncated
- ModelSim Error locally static expression
- Modeling switches without bi-directional buffers
- Counter Question
- generic record exploration.
- case expression and constants
- un-intentional gated clock after synthesis
- no clock signals found ... xilinx ise
- Instantiate primitives in for-generate?
- Remove Duplicate Registers / Logic
- Errors with model sim
- N-input AND gate
- Model Simulation
- VHDL 200X....when?
- Simulating testbench waveform error: "No feasible entries for subprogram write"
- lut
- Decreasing memory size
- Conditional compilation in VHDL
- Keyboard Interface With Handshake
- User-defined global library in ModelSim 6.0?
- ANN: Project VeriPage Announces New SystemVerilog Article
- Overflow detector
- Question about 2 bit counter example.
- How do intel/amd design their processors ?
- Ok cpu designed now what ? ;)
- Main memory <-> Cpu communication ?
- Maximum clock frequency ?
- Bulletproofing CPLD Design
- Re: Question about 2 bit counter example.
- package, component, entity ......
- Re: Question about 2 bit counter example.
- Re: Question about 2 bit counter example.
- Re: Question about 2 bit counter example.
- Re: Maximum clock frequency ?
- assigning delays for bidirectional signals
- Synchronous Serial Port design
- a pipeline with collision detection
- Wait statement
- Multiplexer Index
- ModelSim control
- Legality of type conversion on instance ports?
- what's incorrect ALIAS
- sim_file reading
- CPU <> Memory chip communication interface
- Is it possible to define an alias of a type?
- error in code?
- Convert from std_logic_vector to real
- Dilemna w/ generic port of type array of slv
- Re: CPU <> Memory chip communication interface
- Re: CPU <> Memory chip communication interface
- Re: CPU <> Memory chip communication interface
- Which is faster in ASIC: 2-input AND gate or a 2-input multiplexer
- file lines reading
- Synthesizing high-density designs in Quartus
- Problem in synthesizing function
- process
- avoid latches
- VHDL Goto statement ?
- Re: VHDL Goto statement ?
- What's the best IDE for VHDL so far ? ;)
- ModelSim Error
- Synchronising Reset APP Note
- problem with modelsim
- ANN: Zeus Version 3.95 Editor Released
- I thought that this code compiled, now it does not?
- VHDL200x- Fixed Point Problem in Quartus 5.0
- Vector Slicing in assigments
- problem with timing simulation
- Re: Prob. with EDK 3.2
- Microblaze XPS Gpio not working with interrupts
- is there any way to convert modelsim wave output to text file?
- ROM
- synthesis and sensitivity list?
- converting std_logic_vector to integer
- [Q] transaction
- Dynamic instantiation/removal of TB components?
- FPGA output unreliable
- VHDL-AMS MOS Level3
- C lines To VHDL
- warning when using design compiler
- forcing 1,0 internal signal
- warning in synthesis
- seq. waveform
- image sensor
- Evolutionary VHDL code example
- VHDL-200X Fixed Point Divider
- logic_std and multiply and array index
- PIC18F6520 behavioural model
- String Signal Declaration
- Combinational logic running over multiple clock cycles in Xilinx
- Including Package in VHDL code as reference
- Linear interpolation in vhdl
- problem in timing simulation
- Good SystemC tutorials or books?
- ANN: SystemVerilog Assertion Article on Project VeriPage
- Define Unsigned Type
- Matrix Shifting
- Optimized comparator
- Software simulation of hardware evolution
- Strange FPGA problem
- Re: modelsim error No. vsim-3381, please help me.
- Some design issues on changing from PCI->PCI-Express?
- combinational division
- Help in converting to integer
- convert
- Emulating floating point
- testbench check or wait on signal inside a componen without port declaration
- cpld with low pin count?
- synthese problems
- Start Signal with Zero Value
- Full Array Row
- Free DataSheet Site..
- fast universal compression scheme and its implementation in VHDL
- It urgent for me!!!
- CPLD Powerup RESET
- Integer to SLV type conversion?
- unconstrained structures
- call for Papers, IEEE ISQED 2006
- use clause
- Ripple Clock for a counter
- even or odd
- Tolerant comparator
- How to print std_logic_vector variable into hex string in VHDL
- Null slice? Synthesis in XST?
- Virtex - 4 LC Development Board (DS-KIT-4VLX25LC)
- Synplify warnings
- generate statement
- OEM
- 3D vector
- Vhdl testbench with textio package
- I2C "SCL" line problem
- Metastability or what?
- Help for 4th order runge-kutta VHDL implementation
- Error in clock divider from FAQ
- Finding the execution time
- Read raw binary file
- read hex file in VHDL using modelsim
- Read some hex value in a file for test bench
- firmware version
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- Reading internal signals through a testbench.
- Converting C to VHDL
- Auto allocation of Indexes
- 2D array question
- Shared configurations?
- OpenTech open souce Designs & tools
- state machine implementation (similar states)
- why does std_logic_arith suck?
- type casting vs. type converting
- easy one
- looking for Andrew Rushton
- How widely used is the IEEE numeric_std package?
- How do you save a function result for infinity time?
- How to Stop Modelsim from echoing tcl commands in batch mode?
- Generate simulator commands from waveform
- missing overloaded operator in numeric_std
- tool for graphical scematic design entry?
- Bidirectional bus in Spartan-3
- Multiply using shift, for signed numbers
- Help in controller design
- Two stage pipelining in 16-bit RISC process
- Two stage pipelining in 16-bit RISC process
- Verilog Reference: Thomas & Moorby book
- Verilog Reference: Thomas & Moorby book
- Verilog Reference: Thomas & Moorby book
- Interface VHDL with Java
- [XST] ise6.3i finds FSM and ISE7.1 doesn't, why?
- generate statement
- Ambiguous reference to type
- Directories in script
- not
- VHDL aggregates assignment
- question on timing in synthesizable vhdl
- barrel shifter
- HDL Abstraction of Dynamic Logic
- floppycontroller
- WARNING:HDLParsers:3481
- help-Need Source code or example,control LCD using vhdl
- Looking for a DIgital Systems book with JPEG example code
- Matched Filter for Carrier Recovery
- numeric_std vias std_logic_unsigned
- aclr to FIFO
- How to handle floating inputs in a device?
- Modelsim and Vhdl
- AND or OR function across a vector
- Version Control Software
- VHDL 2005, VHDL93 and FPHDL
- Bus direction
- One Signal Two Names
- Do you still use component declarations?
- Call for papers: EvoHOT 2006 (deadline: 4-Nov)
- modelsim
- Test vector generation for ethernet frame using VHDL
- How to run Modelsim for VHDL without using GUI..
- Passing file name to procedure.
- How to pass a global data type to an entity?
- Modelsim Slice error using numeric_std
- VHDL for problem
- Board Level Bidirectional Connections
- Intialization
- Problem with Behav Sim vs Post Place & Route Sim
- Matrix to vector conversion
- VHDL 2002 differences with 1993?
- type conversation problems
- MAPLD 2005 Postings On-line
- Adding Libraries to Xilinx/ModelSim
- A 64-bit version of conv_std_logic_vector?
- How do you change the Modelsim Cursor Resolution (not simulation resolution)
- Clarification Term: "Behavioural Description"
- can we use two foreign attribute in single module?
- Transaction based testbench - Effective encapsulation of the client 'transactors'?
- Proper organization of function/procedures requiring global signals
- Quartus II 5.0 Web Edition questions
- ModelSim & Signal Spy
- Error :Nonresolved signal 'out1' has multiple sources.
- Initialize array using file i/o procedure/function?
- Nested ifs, why does one work but not the other?
- Accellera, OVL, and VHDL?
- Testbench using Modelsim/VHDL - simple signal generation problem
- cygwin vcom path problems
- Equivalence checkers for clocks
- question on generics, constants in vhdl
- simple synthesis errors
- newbie vhdl question on variable length of '1'
- simulation error
- using reset for arrays
- VCD format with Modelsim
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