View Full Version : VHDL

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  1. Some signals became ? and missing on the simvision, why?
  2. status of language change requests
  3. Ambigous operator '&'
  4. Unconstrained ports for synthesis
  5. Bug in DDR template in Lattice FPGAs ?
  6. Test Vectors of 2's Complement Adder and Substractor /Accumulator/MACs
  7. prfered style of coding?
  8. A question about syntax of VHDL
  9. Converting synthesized VHDL/Verilog to spice netlist
  10. Re: Meine geilen Bilder
  11. Simulation in modelsim.... Multiple Drivers.......
  12. Rising, falling edge
  13. synthesis using the synopsys-Design Vision
  14. Xilinx synthesis problem
  15. Design Configuration
  16. Can real number be synthesized
  17. Construct synthesis problem
  18. fundamental question on process
  19. multiplier one fixed value other user defined
  20. multiplier with one fixed value other user defined
  21. cf FFT
  22. searching for reuse database and archive software
  23. searching for reuse database and archive software
  24. Asynchronous Design
  25. Simulation and realworld problem in design - what is wrong?
  26. ANN: PSL and DPI articles on Project VeriPage
  27. error "choice must be discrete range" with CASE
  28. Testing and finding the error in my design (THINK it's in the presampler/ringbuffer)
  29. Fix point square root
  30. Sync + FIFO
  31. PCI plug n play and Graphics card implementation
  32. dynamic size of ports
  33. How to instantiate identical components by for loop or generate in VHDL?
  34. Synplify warning CL209
  35. Generic in CASE choice ?!?
  36. Creating RAM in VHDL as Project
  37. Flip Flop vs Registers
  38. Signal use from pin
  39. Interfacing Digital Camera
  40. Interfacing Digital Camera
  41. Re: Viterbi Decoder path memory using Block RAM
  42. Variable to signal assignment
  43. post translate simulation
  44. Case statement illusions ?
  45. Register Files for synthesis
  46. Forum VHDL in Italiano
  47. Locally static?!
  48. An easy question for everyone
  49. textio error
  50. Generic, synthesizable synchronous 16x32 FIFO
  51. about "super state machine"
  52. cf_fft
  53. can 2 if's to 1 if save 1 clock cycle?
  54. i2c opencores
  55. Case choice must be a locally static expression.
  56. Latches problem
  57. Text io in Xilinx
  58. Problem in array formation
  59. extension pack
  60. latches again
  61. pulse streatcher
  62. INFO:Xst:1304 -- precise definition anyone?
  63. Linking problem in Primetime
  64. What are these files?
  65. Variable 'variable lengths'
  66. parameterizing number of ports?
  67. Synopsys Design Analyzer in command prompt
  68. HEX to STD_LOGIC_VECTOR
  69. Gezocht: Ervaren VHDL programmeur
  70. MICROBLAZE AND SDRAM
  71. waiting on vector change
  72. cannot be synthesized, bad synchronous description
  73. FSM in VHDL
  74. FSM simulation
  75. Synopsys vhdlsim (VHDL simulator)
  76. Looking for something others
  77. Warning: Output pins are stuck at VCC or GND
  78. VHDL-200x-ft packages
  79. Advanced Synthesis Techniques
  80. Tristate-Master-Slave testbench description
  81. about hdl testbench
  82. State machine transition on internal signals - is it legal?
  83. State machine transition on internal signals -- is it legal?
  84. clockdivider with enable
  85. SDRAM AND MICROBLAZE PART 2
  86. Why do VHDL gate level models simulate slower than verilog
  87. Problem with Clock signals generated by combinational logic
  88. vga controller
  89. wait for signal change
  90. NCSIM simulator
  91. Loop in procedure not complete
  92. Passing a signal from slow to fast clock
  93. Warning:Xst:382 - Register A is equivalent to B
  94. Xilinx ISE : type real
  95. Driving signals from a procedure
  96. Simulation of rocket IO in virtex 2 pro
  97. Good VHDL book for Verilog designer
  98. while condition
  99. Hierarchies not the best for video pipelines
  100. dlx to three stages
  101. Process Statements in VHDL
  102. FSM with more than 1 input at each state
  103. 8bit counter to 7seg
  104. 1732074 CD-R, DVD R, DVD CASES LOWEST PRICE! 17
  105. Signed Adder without overflow
  106. Bit stuffing in a Crc encoder
  107. assert/report problems
  108. Unconstrained array for output port in generic :/
  109. ARM LINKS ANS DOCUMENTAION OF THE ARCHITECTURE
  110. VHDL-200x-FT Place&Route problem in Quartus II
  111. "else process" clause
  112. 24 bit signed multiplier
  113. FATAL_ERROR:Xst:xstedge.c:128:1.4 ???
  114. matched delays in Xilinx ISE?
  115. ANN: Project VeriPage Update - New articles on SystemVerilog and PSL
  116. Help - Simulator CBS.
  117. bit vs std_logic ?
  118. process getting called more than once
  119. parallel CRC equation generator
  120. pass an undefined number of datasets
  121. real to integer conversion
  122. Xilinx synthesis warning regarding clock nets
  123. HOLD warning? Please comment on my code!
  124. help with serial to parallel conversion inside the fpga
  125. Help with state mahine resets
  126. SRAM access times
  127. how to in INSTANTIATING large number of components?
  128. extension_pack
  129. why FSM so big
  130. 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
  131. Spartan 3 Starter Kit group formed
  132. wierd memory description
  133. AHDL graphic State Diagram and adding my own "type"
  134. Fast/low area Sorting hardware.
  135. VHDL Code Metrics
  136. Codec Video on FPGA
  137. VHDL -> PCB netlist ?
  138. edif2ngd warning
  139. Q, howto setup 'unisim' for modelsim in linux
  140. an error on multi-source, but I can't understand...
  141. new to VHDL needs help
  142. How to make a loop correctly?
  143. AVR core and patents
  144. I2C slave clock stretching
  145. fast universal compression scheme and its implementation in VHDL
  146. VHDL boolean representation
  147. Increasing the Global Clock value inside the design ?
  148. hlp_needed in VHDL
  149. single wire serial comms module
  150. VHDL-200x fixed point package takes very long to synthesize
  151. Help with syntesis warnings
  152. Out of range on type real?
  153. Turbo Decoder IP Core
  154. VHDL-AMS problem
  155. component port mapping
  156. binary to decimal
  157. FIFO simulation
  158. design boolean equations
  159. Sensitivity list
  160. N-Input Gate Using Loop or Generate
  161. Need standard function to do (Bool and Vector)
  162. modeling connecting Processor with memory
  163. modeling connecting Processor with memory
  164. 1-element arrays are invalid in VHLD?
  165. another array ranges mystery
  166. Books: Verilog and VHDL
  167. Post Translate Timing
  168. Altera SCFIFO
  169. Bad synchronous description, but why ?
  170. Where is the bug?
  171. VHDL-plugin for jedit sidekick?
  172. Help: what does this VHDL code mean?
  173. DC vhdl question
  174. about addition operator
  175. comparing the contents of memory
  176. exiting from state machine
  177. Need help with AHDL
  178. What does this AHDL code mean?
  179. [koma] [titlepage] Anschrift Links, Logo rechts
  180. Array's of files
  181. ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL
  182. Reading hex data from file
  183. Problem in design
  184. vhdl model length of wire with delay ?
  185. Log implementation in vhdl
  186. YOU ALL NEED TO SEE THIS JAW DROPPING PROOF THAT THE U.S. ADMINISTRATION WAS 100 % BEHIND THE SEPT 11 ATTACKS
  187. verilog to vhdl translation
  188. Uart and clock
  189. Event counters for simulation only
  190. Converting logic_vector -> natural
  191. How to save line in VHDL?
  192. array in vhdl
  193. Or'ing output from conditionally generated instances
  194. Synopsys clock edge question
  195. Modelsim breakpoint on end process.
  196. comparing the array in parallel
  197. Specifying vector length in the function output
  198. 'inout' procedure signal
  199. attribute signal name
  200. comparing the array for generic parameters
  201. while loop
  202. Hex files in simulation
  203. netlist from VHDL code
  204. netlist from VHDL code
  205. code error
  206. TK simulation for 2-line LCD panel
  207. Integer to std_logic_vector?
  208. problem in my code
  209. Subtyping issue
  210. Sequential Circuits power up Reset
  211. memory creation with record
  212. model sim error in my design
  213. vhdl source cross-referencing tool
  214. mandatory output binding?
  215. Q, logic value 'X'
  216. model sim errors in my design
  217. to access an array defined in some other file ?
  218. Intialization of State machine
  219. COMPILATION ERROR
  220. fphdl package compilation error in Modelsim
  221. help conversion code
  222. help conversion code right one
  223. Active Conferences?
  224. Error Solving
  225. Digital Down synthetizer
  226. configuration error
  227. Compile model error
  228. Basic VHDL question regarding pins
  229. modelsim warnings
  230. Generic shift register where value 'n' keeps changing
  231. About AC97 audio controller
  232. signal assigning question in FSM
  233. reading synchronous RAM asynchronously?
  234. verilog module instantantiation in VHDL top level
  235. VHDL-beginner question: output-value isn't stored
  236. Help with advanced generic model
  237. Detecting end of file for VHDL'93
  238. aggregate operator
  239. Bazix introduce One Chip FPGA computer
  240. Xilinx Conversion 3.1 --> 6.1
  241. Reading from STDIN for simulation
  242. instances of entities vs components
  243. MAPLD 2005: Program Announced and Registration Open
  244. Floating point synthesis
  245. PACKAGE MATH_REAL problems
  246. State Machine Approaches - A Revisit
  247. Array of generic width std_logic_vector in entity?
  248. morre model
  249. Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
  250. Question regarding pragma translate_off/on , synthesis_off/on