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- Some signals became ? and missing on the simvision, why?
- status of language change requests
- Ambigous operator '&'
- Unconstrained ports for synthesis
- Bug in DDR template in Lattice FPGAs ?
- Test Vectors of 2's Complement Adder and Substractor /Accumulator/MACs
- prfered style of coding?
- A question about syntax of VHDL
- Converting synthesized VHDL/Verilog to spice netlist
- Re: Meine geilen Bilder
- Simulation in modelsim.... Multiple Drivers.......
- Rising, falling edge
- synthesis using the synopsys-Design Vision
- Xilinx synthesis problem
- Design Configuration
- Can real number be synthesized
- Construct synthesis problem
- fundamental question on process
- multiplier one fixed value other user defined
- multiplier with one fixed value other user defined
- cf FFT
- searching for reuse database and archive software
- searching for reuse database and archive software
- Asynchronous Design
- Simulation and realworld problem in design - what is wrong?
- ANN: PSL and DPI articles on Project VeriPage
- error "choice must be discrete range" with CASE
- Testing and finding the error in my design (THINK it's in the presampler/ringbuffer)
- Fix point square root
- Sync + FIFO
- PCI plug n play and Graphics card implementation
- dynamic size of ports
- How to instantiate identical components by for loop or generate in VHDL?
- Synplify warning CL209
- Generic in CASE choice ?!?
- Creating RAM in VHDL as Project
- Flip Flop vs Registers
- Signal use from pin
- Interfacing Digital Camera
- Interfacing Digital Camera
- Re: Viterbi Decoder path memory using Block RAM
- Variable to signal assignment
- post translate simulation
- Case statement illusions ?
- Register Files for synthesis
- Forum VHDL in Italiano
- Locally static?!
- An easy question for everyone
- textio error
- Generic, synthesizable synchronous 16x32 FIFO
- about "super state machine"
- cf_fft
- can 2 if's to 1 if save 1 clock cycle?
- i2c opencores
- Case choice must be a locally static expression.
- Latches problem
- Text io in Xilinx
- Problem in array formation
- extension pack
- latches again
- pulse streatcher
- INFO:Xst:1304 -- precise definition anyone?
- Linking problem in Primetime
- What are these files?
- Variable 'variable lengths'
- parameterizing number of ports?
- Synopsys Design Analyzer in command prompt
- HEX to STD_LOGIC_VECTOR
- Gezocht: Ervaren VHDL programmeur
- MICROBLAZE AND SDRAM
- waiting on vector change
- cannot be synthesized, bad synchronous description
- FSM in VHDL
- FSM simulation
- Synopsys vhdlsim (VHDL simulator)
- Looking for something others
- Warning: Output pins are stuck at VCC or GND
- VHDL-200x-ft packages
- Advanced Synthesis Techniques
- Tristate-Master-Slave testbench description
- about hdl testbench
- State machine transition on internal signals - is it legal?
- State machine transition on internal signals -- is it legal?
- clockdivider with enable
- SDRAM AND MICROBLAZE PART 2
- Why do VHDL gate level models simulate slower than verilog
- Problem with Clock signals generated by combinational logic
- vga controller
- wait for signal change
- NCSIM simulator
- Loop in procedure not complete
- Passing a signal from slow to fast clock
- Warning:Xst:382 - Register A is equivalent to B
- Xilinx ISE : type real
- Driving signals from a procedure
- Simulation of rocket IO in virtex 2 pro
- Good VHDL book for Verilog designer
- while condition
- Hierarchies not the best for video pipelines
- dlx to three stages
- Process Statements in VHDL
- FSM with more than 1 input at each state
- 8bit counter to 7seg
- 1732074 CD-R, DVD R, DVD CASES LOWEST PRICE! 17
- Signed Adder without overflow
- Bit stuffing in a Crc encoder
- assert/report problems
- Unconstrained array for output port in generic :/
- ARM LINKS ANS DOCUMENTAION OF THE ARCHITECTURE
- VHDL-200x-FT Place&Route problem in Quartus II
- "else process" clause
- 24 bit signed multiplier
- FATAL_ERROR:Xst:xstedge.c:128:1.4 ???
- matched delays in Xilinx ISE?
- ANN: Project VeriPage Update - New articles on SystemVerilog and PSL
- Help - Simulator CBS.
- bit vs std_logic ?
- process getting called more than once
- parallel CRC equation generator
- pass an undefined number of datasets
- real to integer conversion
- Xilinx synthesis warning regarding clock nets
- HOLD warning? Please comment on my code!
- help with serial to parallel conversion inside the fpga
- Help with state mahine resets
- SRAM access times
- how to in INSTANTIATING large number of components?
- extension_pack
- why FSM so big
- 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
- Spartan 3 Starter Kit group formed
- wierd memory description
- AHDL graphic State Diagram and adding my own "type"
- Fast/low area Sorting hardware.
- VHDL Code Metrics
- Codec Video on FPGA
- VHDL -> PCB netlist ?
- edif2ngd warning
- Q, howto setup 'unisim' for modelsim in linux
- an error on multi-source, but I can't understand...
- new to VHDL needs help
- How to make a loop correctly?
- AVR core and patents
- I2C slave clock stretching
- fast universal compression scheme and its implementation in VHDL
- VHDL boolean representation
- Increasing the Global Clock value inside the design ?
- hlp_needed in VHDL
- single wire serial comms module
- VHDL-200x fixed point package takes very long to synthesize
- Help with syntesis warnings
- Out of range on type real?
- Turbo Decoder IP Core
- VHDL-AMS problem
- component port mapping
- binary to decimal
- FIFO simulation
- design boolean equations
- Sensitivity list
- N-Input Gate Using Loop or Generate
- Need standard function to do (Bool and Vector)
- modeling connecting Processor with memory
- modeling connecting Processor with memory
- 1-element arrays are invalid in VHLD?
- another array ranges mystery
- Books: Verilog and VHDL
- Post Translate Timing
- Altera SCFIFO
- Bad synchronous description, but why ?
- Where is the bug?
- VHDL-plugin for jedit sidekick?
- Help: what does this VHDL code mean?
- DC vhdl question
- about addition operator
- comparing the contents of memory
- exiting from state machine
- Need help with AHDL
- What does this AHDL code mean?
- [koma] [titlepage] Anschrift Links, Logo rechts
- Array's of files
- ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL
- Reading hex data from file
- Problem in design
- vhdl model length of wire with delay ?
- Log implementation in vhdl
- YOU ALL NEED TO SEE THIS JAW DROPPING PROOF THAT THE U.S. ADMINISTRATION WAS 100 % BEHIND THE SEPT 11 ATTACKS
- verilog to vhdl translation
- Uart and clock
- Event counters for simulation only
- Converting logic_vector -> natural
- How to save line in VHDL?
- array in vhdl
- Or'ing output from conditionally generated instances
- Synopsys clock edge question
- Modelsim breakpoint on end process.
- comparing the array in parallel
- Specifying vector length in the function output
- 'inout' procedure signal
- attribute signal name
- comparing the array for generic parameters
- while loop
- Hex files in simulation
- netlist from VHDL code
- netlist from VHDL code
- code error
- TK simulation for 2-line LCD panel
- Integer to std_logic_vector?
- problem in my code
- Subtyping issue
- Sequential Circuits power up Reset
- memory creation with record
- model sim error in my design
- vhdl source cross-referencing tool
- mandatory output binding?
- Q, logic value 'X'
- model sim errors in my design
- to access an array defined in some other file ?
- Intialization of State machine
- COMPILATION ERROR
- fphdl package compilation error in Modelsim
- help conversion code
- help conversion code right one
- Active Conferences?
- Error Solving
- Digital Down synthetizer
- configuration error
- Compile model error
- Basic VHDL question regarding pins
- modelsim warnings
- Generic shift register where value 'n' keeps changing
- About AC97 audio controller
- signal assigning question in FSM
- reading synchronous RAM asynchronously?
- verilog module instantantiation in VHDL top level
- VHDL-beginner question: output-value isn't stored
- Help with advanced generic model
- Detecting end of file for VHDL'93
- aggregate operator
- Bazix introduce One Chip FPGA computer
- Xilinx Conversion 3.1 --> 6.1
- Reading from STDIN for simulation
- instances of entities vs components
- MAPLD 2005: Program Announced and Registration Open
- Floating point synthesis
- PACKAGE MATH_REAL problems
- State Machine Approaches - A Revisit
- Array of generic width std_logic_vector in entity?
- morre model
- Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
- Question regarding pragma translate_off/on , synthesis_off/on
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